參數(shù)資料
型號(hào)： MB90V330A
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 82/116頁
文件大?。?/td> 632K
代理商： MB90V330A
MB90330 Series
82
20. Low power consumption (standby) mode
The F
2
MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode.
CPU operation mode and functional description
CPU
operating
clock
Register list
Operation
mode
Description
PLL clock
Normal runThe CPU and peripheral resources operate at the clock frequency obtained by PLL
multiplication of oscillator clock (HCLK) frequency.
Sleep
Only peripheral resources operate at the clock frequency obtained by PLL multiplica-
tion of the oscillator clock (HCLK) .
Time-base
timer
Only the time-base timer operates at the clock frequency obtained by PLL multiplica-
tion of the oscillator clock (HCLK) frequency.
Stop
The CPU and peripheral resources are suspended with the oscillator clock stopped.
Main clock
Normal runThe CPU and peripheral resources operate at the clock frequency obtained by divid-
ing the oscillator clock (HCLK) frequency by two.
Sleep
Only peripheral resources operate at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Time-base
timer
Only the time-base timer operates at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Stop
The CPU and peripheral resources are suspended with the oscillator clock stopped.
Sub clock
Normal runThe CPU and peripheral resources operate at the clock frequency obtained by
dividing the subclock (SCLK) frequency by four.
Sleep
Only peripheral resources operate at the clock frequency obtained by dividing the
subclock (SCLK) frequency by four.
Watch
mode
Only the watch timer operates at the clock frequency obtained by dividing the
subclock (SCLK) frequency by four.
Stop
The CPU and peripheral resources are suspended with the subclock stopped.
CPU
intermittent
operation
mode
Normal runThe halved or PLL-multiplied oscillator clock (HCLK) frequency or the subclock
(SCLK) frequency is used for operation while being decimated in a certain period.
Low power consumption mode control register (LPMCR)
Initial Value
00011000
B
Address : 0000A0
H
( W )
( R/W )
( W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
SLP
( W )
STP
SPL
RST
TMD
CG1
CG0
Reserved
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