
MB90330 Series
79
17. Address matching detection function
When the address is equal to the value set in the address detection register, the instruction code to be read into
the CPU is forcibly replaced with the INT9 instruction code (01
H
). As a result, the CPU executes the INT9
instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the
program patch function is enabled.
2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address
matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code
to be read into the CPU is forcibly replaced with the INT9 instruction code.
Register list
Program address detect register 0 to 2 (PADR0)
PADR0 (lower)
Program address detect register 3 to 5 (PADR1)
PADR1 (lower)
Program address detection control status register (PACSR)
PACSR
7
Initial Value
XXXXXXXX
B
Address : 001FF0
H
PADR0 (middle)
Initial Value
XXXXXXXX
B
Address : 001FF1
H
PADR0 (upper)
Initial Value
XXXXXXXX
B
Address : 001FF2
H
Initial Value
XXXXXXXX
B
Address : 001FF3
H
PADR1 (middle)
Initial Value
XXXXXXXX
B
Address : 001FF4
H
PADR1 (upper)
Initial Value
XXXXXXXX
B
Address : 001FF5
H
Initial Value
00000000
B
Address : 00009E
H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
6
5
4
3
2
1
0
(R/W)
ADIE
ADDE
Reserved Reserved Reserved Reserved
Reserved
Reserved
R/W : Readable and Writable
X
: Undefined