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參數(shù)資料
| 型號(hào)： | MB90V330A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專(zhuān)有 |
| 文件頁(yè)數(shù)： | 76/116頁(yè) |
| 文件大小： | 632K |
| 代理商： | MB90V330A |
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MB90330 Series
76
15.
μ
DMAC
μ
DMAC is simple DMA with the function equal with EI
2
OS. It has 16 channels DMA transfer channels with the
following features.
Performs automatic data transfer between the peripheral resource (I/O) and memory
The program execution of CPU stops in the DMA start-up
Capable of selecting whether to increment the transfer source and destination addresses
DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and
descriptor.
A STOP request is available for stopping DMA transfer from the resource.
Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA
status register is set and a termination interrupt is output to the transfer controller.
Register list
(Continued)
DMA enable register upper (DERH)
DMA enable register lower (DERL)
DMA stop status register (DSSR)
DMA status register upper (DSRH)
DMA status register lower (DSRL)
DMA descriptor channel specification register (DCSR)
* : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”.
The DSSR is upper when the STP bit of DCSR in the DSSR is “1”.
Initial Value
00000000
B
Address : 0000AD
H
Initial Value
00000000
B
Address : 0000AC
H
Initial Value
00000000
B
Address : 0000A4
H
*
Initial Value
00000000
B
Address : 00009D
H
Initial Value
00000000
B
Address : 00009C
H
Initial Value
00000000
B
Address : 00009B
H
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
EN14
( R/W )
EN15
EN13
EN12
EN11
EN10
EN9
EN8
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
EN6
( R/W )
EN7
EN5
EN4
EN3
EN2
EN1
EN0
7
6
5
4
3
2
1
0
STP6
STP14
( R/W )
STP7
STP15
( R/W )
STP5
STP13
( R/W )
STP4
STP12
( R/W )
STP3
STP11
( R/W )
STP2
STP10
( R/W )
STP1
STP9
( R/W )
STP0
STP8
( R/W )
15
14
13
12
11
10
9
8
DTE14
DTE15
DTE13
DTE12
DTE11
DTE10
DTE9
DTE8
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
DTE6
( R/W )
DTE7
DTE5
DTE4
DTE3
DTE2
DTE1
DTE0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
( R/W )
STP
DCSR3 DCSR2
DCSR1 DCSR0
Reserved Reserved Reserved
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