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參數(shù)資料
| 型號： | MB90V330A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 41/116頁 |
| 文件大小： | 632K |
| 代理商： | MB90V330A |
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MB90330 Series
41
3.
Watchdog timer
The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating
with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is
not cleared for a preset period of time after start.
Interval time of watchdog timer
Notes :
The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.
The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or
watch timer.
Interval time of watchdog timer is longer than the set time during the following conditions.
- When clearing the timebase timer during operation on oscillation (HCLK)
- When clearing the watch timer during operation on sub clock (SCLK)
Events that stop the watchdog timer
Stop due to a power-on reset
Watchdog reset
Clear factor of watchdog timer
External reset input by RST pin
Writing “0” to the software reset bit
Writing “0” to the watchdog timer control bit (second and subsequent times)
Transition to sleep mode (clearing the watchdog timer to suspend counting)
Transition to time-base timer mode (clearing the watchdog timer to suspend counting)
Transition to stop mode (clearing the watchdog timer to suspend counting)
HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 KHz)
Min
Max
Clock cycle
2
14
±
2
11
/
HCLK
2
16
±
2
13
/
HCLK
2
18
±
2
15
/
HCLK
2
21
±
2
18
/
HCLK
2
12
±
2
9
/
SCLK
2
15
±
2
12
/
SCLK
2
16
±
2
13
/
SCLK
2
17
±
2
14
/
SCLK
Approx. 2.39 ms
Approx. 3.07 ms
Approx. 9.56 ms
Approx. 12.29 ms
Approx. 38.23 ms
Approx. 49.15 ms
Approx. 305.83 ms
Approx. 393.22 ms
Approx. 0.448 s
Approx. 0.576 s
Approx. 3.584 s
Approx. 4.608 s
Approx. 7.168 s
Approx. 9.216 s
Approx. 14.336 s
Approx. 18.432 s
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