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參數(shù)資料
| 型號(hào)： | MB90V330A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專(zhuān)有 |
| 文件頁(yè)數(shù)： | 46/116頁(yè) |
| 文件大?。?/td> | 632K |
| 代理商： | MB90V330A |
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MB90330 Series
46
6.
Multi function timer
The multi-function timer enables the following based on the 16-bit free-run timer.
Output of independent waveform
Measurement of input pulse width
Measurement of external clock cycle
Configuration of a multi-functional timer
16-bit free-run timer 16-bit Output Compare 16-bit Input Capture 8/16-bit PPG timer 16-bit PWC timer
16-bit free-run timer : 1 channel
The 16-bit free-run timer consists of a 16-bit up counter (timer data register (TCDT)), compare clear register
(CPCLR), timer control status register (TCCS), and prescaler.
The counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input
capture units.
The count clock can be set, selected from among the following eight types.
1/
φ
, 2/
φ
, 4/
φ
, 8/
φ
, 16/
φ
, 32/
φ
, 64/
φ
, 128/
φ
φ
: Machine clock frequency
During the following conditions, the interrupt should be output.
- The counter value of 16-bit free run timer will be overflowed.
- The counter value of 16-bit free run timer will be cleared after the counter value of 16-bit free run timer
=
the
compare clear register value (CPCLR) (TCCS : ICRE
=
“1”, MODE
=
“1”)
The counter value of 16-bit free run timer should be cleared to “0000
H
” during the following conditions.
Reset
When setting the clear bit (SCLR) of timer control status register (TCCS) to “1”
When the counter value of the 16-bit free run timer
=
the compare clear register value (CPCLR) (TCCS :
MODE
=
“1”)
When setting “0000
H
” to the timer data register (TCDT)
Output compare : 4 channels
The output compare unit consists of compare registers (OCCP0 to OCCP3), compare control registers (OCS0
to OCS3), and a compare output latch.
The output compare unit can invert the output level and output an interrupt when a compare register (OCCP0
to OCCP3) value matches the counter value of the 16-bit free-run timer.
Output compare registers can operate as 4 independent channels. The compare registers (OCCP0 to OCCP3)
of each channel have interrupt request flags of their respective output pins.
Pin output can be inverted by using 2 channels of compare registers (OCCP0 to OCCP3).
If the counter value of 16-bit free run timer
=
the compare register (OCCP0 to OCCP3) (OCS0, OCS2 :
IOP0
=
“1”, IOP1
=
“1”), the interrupt request should be generated.
The initial value for pin output of each channel can be set.
Input capture : 4 channels
The input capture unit consists of the input capture data registers (IPCP0 to IPCP3) corresponding to external
input pins (IN0 to IN3) and input capture control registers (ICS01, ICS23).
The input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data
register (IPCP0 to IPCP3) to generated an interrupt request upon detection of the effective edge of the signal
input through the external input.
1 channel
4 channels
4 channels
8-bit
×
6 channels
(16-bit
×
3 channels)
1 channel
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