參數(shù)資料
型號: MB90T673
廠商: Fujitsu Limited
英文描述: Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 81/124頁
文件大小: 2584K
代理商: MB90T673
81
MB90670/675 Series
(3) Clock Timing
Operation at 5.0 V
±
10%
(AV
SS
= V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
Unit
Min.
Typ.
Max.
3
32
31.25
333
* :The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
The PLL frequency deviation changes periodically from the preset frequency “(about CLK
×
(1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
Parameter
Symbol
Pin name Condition
Remarks
Clock frequency
Clock cycle time
F
C
t
C
X0, X1
X0, X1
MHz
ns
Input clock pulse width
P
WH
,
P
WL
X0
10
ns
Recommended
duty ratio of
30% to 70%
Input clock rising/falling time
t
CR
,
t
CF
X0
5
ns
Internal operating clock
frequency
Internal operating clock cycle
time
Frequency fluctuation rate
locked
f
CP
1.5
16
MHz
t
CP
62.5
666
ns
f
P37/CLK
3
%
*
α
|
f
O
Center frequency
+
+
α
f
O
α
f = |
×
100 (%)
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