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參數(shù)資料
| 型號： | MB90T673 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 71/124頁 |
| 文件大小： | 2584K |
| 代理商： | MB90T673 |
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71
MB90670/675 Series
15. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
Minimum conversion time: 6.13
μ
s (at machine clock of 16 MHz, including sampling time)
Minimum sampling time: 3.75
μ
s (at machine clock of 16 MHz)
Conversion method: RC successive approximation method with a sample and hold circuit.
Resolution: 10-bit or 8-bit selective
Analog input pins: Selectable from eight channels by software
One-shot conversion mode:Stops conversion after completing a conversion for a stopped channel (one
channel only) or for successive channels (maximum of eight channels can be
specified)
Continuous conversion mode:Continues conversions for a specified channel (one channel only) or for
successive channels (maximum of eight channels can be specified)
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation.
Interrupt requests can be generated and the extended intelligent I/O service (EI
2
OS) can be started after the
end of A/D conversion.
When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
Starting factors for conversion: Selected from software activation, 16-bit reload timer 1 output (rising edge),
and external trigger (falling edge).
(1) Register Configuration
A/D control status register upper digits (ADCS: H)
Address
bit 15
bit 14
00002D
H
bit 7 . . . . . . .. . . . .
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
RESV
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
(ADCS: L)
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
Address
00002C
H
bit 15 . . . . . . .. . . . .
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
(ADCS: H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
A/D control status register lower digits (ADCS: L)
Address
00002E
H
S10
A/D data register (ADCR)
—
—
—
—
—
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
bit 15bit 14 bit 13 bit 12bit 11 bit 10
bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W
—
—
—
—
—
R
R
R
R
R
R
R
R
R
R
Initial value
00000000
B
Initial value
00000000
B
Initial value
XXXXXXXX
B
0000000X
B
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