參數(shù)資料
型號: MB90T673
廠商: Fujitsu Limited
英文描述: Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 69/124頁
文件大?。?/td> 2584K
代理商: MB90T673
69
MB90670/675 Series
13. Wake-up Interrupt
Wake-up interrupts transmits interrupt request (“L” level) generated by peripheral device located between
external peripheral devices and the F
2
MC-16L CPU to the CPU and invokes interrupt processing.
The interrupt does not conform to the extended intelligent I/O service (EI
2
OS).
(1) Register Configuration
(2) Block Diagram
bit 7 .. . . . . . .. . . .
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Wake-up interrupt flag register (EIFR)
Address
00000F
H
WIF
(Vacancy)
Initial value
- - - - - - - 0
B
R/W: Readable and writable
— : Unused
R/W
Wake-up interrupt enable register (EICR)
bit 15
Address
00001F
H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
(Vacancy)
bit 7 .. . . . . . .. . . .
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P10/AD08/WI0
Pin
Wake-up interrupt
enable register (EICR)
Interrupt request detection circuit
Internal data bus
Wake-up interrupt flag
register (EIFR)
*: Interrupt number
Wake-up interrupt
request
#33 (21
H
)*
Pin
Pin
Pin
Pin
Pin
Pin
Pin
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
WIF
P11/AD09/WI1
P12/AD10/WI2
P13/AD11/WI3
P14/AD12/WI4
P15/AD13/WI5
P16/AD14/WI6
P17/AD15/WI7
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