參數(shù)資料
型號(hào)： MB90T673
廠商： Fujitsu Limited
英文描述： Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125
中文描述： 16位微控制器專有
文件頁數(shù)： 63/124頁
文件大小： 2584K
代理商： MB90T673
63
MB90670/675 Series
10. UART0
UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous
communication (start-stop synchronization system). In addition to the normal duplex communication function
(normal mode), UART0 has a master/slave type communication function (multi-processor mode).
Data buffer: Full-duplex double buffer
Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
Baud rate: With dedicated baud rate generator, selectable from 12 types
External clock input possible
Internal clock (a clock supplied from 16-bit reload timer can be used.)
Data length: 7 bits to 9 bits selective (with a parity bit)
6 bits to 8 bits selective (without a parity bit)
Signal format: NRZ (Non Return to Zero) system
Reception error detection: Framing error
Overrun error
Parity error (not available in multi-processor mode)
Interrupt request: Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI
2
OS)
Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication
possible
(1) Register Configuration
Status register 0 (USR0)
RDRF ORFE
R/W
PE
R/W
TDRE
R/W
RIE
R/W
TIE
R/W
RBF
R/W
TBF
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Address
000021
H
Initial value
00100000
B
(UMC0)
bit 7. .. . . . . . .. . . .
Mode control register 0 (UMC0)
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
000020
H
Initial value
00000100
B
(USR0)
bit 15.. . . . . . .. . . .
Rate and data register 0 (URD0)
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Address
000023
H
Initial value
00000000
B
(UIDR0/UODR0)
bit 7. .. . . . . . .. . . .
Input data register 0 (UIDR0)
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
000022
H
Initial value
XXXXXXXX
B
(URD0)
bit 15.. . . .
bit 8
D8
R
Output data register 0 (UODR)
Address
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000022
H
Initial value
XXXXXXXX
B
(URD0)
bit 15.. . . .
bit 8
D8
W
R/W : Readable and writable
R : Read only
W : Write only
X
: Indeterminate
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