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參數(shù)資料
| 型號(hào)： | MB90P634APF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 69/107頁(yè) |
| 文件大小： | 1599K |
| 代理商： | MB90P634APF |
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64
MB90630A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1) Register Configuration
(2) Register Details
Delayed interrupt request register (DIRR)
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(3) Block Diagram
00009FH
15
14
13
12
11
10
9
——————
—
R0
8
Address:
bit
Delayed interrupt request register
(DIRR)
00009FH
15
14
13
12
11
10
9
——————
—
R0
8
Address:
bit
Initial value
-------0 B
(R/W)
Delayed interrupt generate/clear decoder
Interrupt latch
F
2
MC-16
bus
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