
25
MB90630A Series
(Continued)
Address
Register
name
Access
Resource
Initial value
51H
Upper compare register channel 0
OCCP0
R/W
16-bit I/O timer
Output compare
(channel 0 to 3)
XXXXXXXX
52H
Lower compare register channel 1
OCCP1
R/W
XXXXXXXX
53H
Upper compare register channel 1
XXXXXXXX
54H
Lower compare register channel 2
OCCP2
R/W
XXXXXXXX
55H
Upper compare register channel 2
XXXXXXXX
56H
Lower compare register channel 3
OCCP3
R/W
XXXXXXXX
57H
Upper compare register channel 3
XXXXXXXX
58H
Compare control status register channel 0
OCS0
R/W
– ––00000
59H
Compare control status register channel 1
OCS1
R/W
0 000––00
5AH
Compare control status register channel 2
OCS2
R/W
– ––00000
5BH
Compare control status register channel 3
OCS3
R/W
0 000––00
5C to 5FH
Reserved area
60H
Lower input capture register channel 0
IPCP0
R
16-bit I/O timer
Input capture
(channel 0, 1)
XXXXXXXX
61H
Upper input capture register channel 0
R
XXXXXXXX
62H
Lower input capture register channel 1
IPCP1
R
XXXXXXXX
63H
Upper input capture register channel 1
R
XXXXXXXX
64H
Input capture control status register
ICS
R/W
0 0 0 0 0 0 0 0
65H
Reserved area
—
––––––––
66H
Lower timer data register
TCDTL
R/W
16-bit I/O timer
Free-run timer
(channel 0, 1)
00000000
67H
Upper timer data register
TCDTH
R/W
0 0 0 0 0 0 0 0
68H
Timer control status register
TCCS
R/W
0 0 0 0 0 0 0 0
69 to 6FH
Reserved area
70H
Up/down count register channel 0
UDCR0
R
8/16-bit up/down
timer/counter
00000000
71H
Up/down count register channel 1
UDCR1
0 0 0 0 0 0 0 0
72H
Reload compare register channel 0
RCR0
W
00000000
73H
Reload compare register channel 1
RCR1
0 0 0 0 0 0 0 0
74H
Counter status register channel 0
CSR0
R/W
0 0 0 0 0 0 0 0
75H
Reserved area
—
––––––––
76H
Counter control register channel 0
CCRL0
R/W
–0000000
77H
CCRH0
0 0000000
78H
Counter status register channel 1
CSR1
R/W
0 0 0 0 0 0 0 0
79H
Reserved area
—
––––––––
7AH
Counter control register channel 1
CCRL1
R/W
– 0 0 0 0 0 0 0