參數(shù)資料
型號(hào)： MB90P634APF
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 55/107頁(yè)
文件大小： 1599K
代理商： MB90P634APF
51
MB90630A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, four output compare, and two input capture modules.
Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs
and to measure input pulse widths and external clock periods.
(1) A Summary of Each Function
16-bit free-run timer (
× 1)
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the
timer/counter is used as the base time for the input capture and output compare.
(a) The operating clock for the counter can be selected from four different clocks.
Four internal clocks (
φ/4, φ/16, φ/32, φ/64)
(b) Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs
(the appropriate mode must be set for a compare match).
(c) The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0.
Output compare (
× 4)
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches
the compare register value.
(a) The four compare registers can be operated independently.
Each compare register has a corresponding output pin and interrupt flag.
(b) The four compare registers can be paired to control the output pins.
Invert the output pins using the four compare registers.
(c) Initial values can be set for the output pins.
(d) An interrupt can be generated when a compare match occurs.
Input capture (
× 2)
The input capture consists of two independent external input pins, their corresponding capture registers, and a
control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
(a) The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
(b) The two input capture channels can operate independently.
(c) An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
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