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MB90630A Series
3. I/O Expansion Serial Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSB-
first or MSB-first data transfer can be selected.
The following two serial I/O operation modes are available.
Internal shift clock mode: Data transfer is synchronized with the internal clock.
External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By
manipulating the general-purpose port that shares the external pin (SCK), this
mode also enables the data transfer operation to be driven by CPU instructions.
(1) Register Configuration
(2) Register Details
Serial Mode Control Status Register (SMCS)
*1: Only “0” can be written.
*2: Only “1” can be written. Reading always returns “0”.
This register controls the transfer operation mode of the serial I/O. The following describes the function of each
bit.
(a) [bit 3] Serial mode selection bit (MODE)
This bit selects the conditions for starting operation from the halted state. Changing the mode during operation
is prohibited.
The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O
service.
MODE
Operation
0
Start when STRT is set to “1”. [Initial value]
1
Start on reading from or writing to the serial data register.
SMD2 SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
15
14
13
12
11
10
9
8
—
MODE
BDS
SOE
SCOE
7
6
5
4
321
0
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
321
0
Address: 000025H
000029H
Address: 000024H
000028H
Address: 000026H
00002AH
bit
Serial mode control status
registers 0, 1 (SMCS0, 1)
Serial data registers 0, 1
(SDR0, 1)
SMD2 SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
15
14
13
12
11
10
9
8
—
MODE
BDS
SOE
SCOE
7
6
5
4
321
0
SMCS
bit
Initial value
00000010B
----0000B
Address: 000025H
000029H
Address: 000024H
000028H
Initial value
(R/W)
(R/W) (R/W*1)
(R)
(R/W)
(R/W*2)