參數(shù)資料
型號(hào)： MB90F523B
廠商： Fujitsu Limited
英文描述： Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125
中文描述： 16位微控制器專有
文件頁(yè)數(shù)： 65/99頁(yè)
文件大?。?/td> 978K
代理商： MB90F523B
MB90520A/520B Series
65
15. Clock Timer
The clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock.
Seven different interval time settings are available.
This timer provides the clock for the sub-clock’s oscillation stabilization delay timer and the watchdog timer.
This timer always counts the sub-clock, regardless of the settings in the clock selection register (CKSC) .
Clock timer functions
Clock timer interval times
Sub-Clock Period
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
Clock periods generated by clock timer
Clock Supply
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
Function
Interval time
Selectable from the seven settings shown in the table below.
15-bit
Oscillation stabilization delay timer for sub-clock and watchdog timer
Sub-oscillation clock divided by four. (SCLK : Sub-clock)
Interval time overflow
Not supported by the extended intelligent I/O service (EI
2
OS) .
Clock timer size
Clock supply
Source clock
Interrupts
EI
2
OS support
Interval Time
SCLK (122
μ
s)
2
9
/SCLK (approx. 62.5 ms)
2
10
/SCLK (approx. 125.0 ms)
2
11
/SCLK (approx. 250.0 ms)
2
12
/SCLK (approx. 500.0 ms)
2
13
/SCLK (approx. 1.0 s)
2
14
/SCLK (approx. 2.0 s)
2
16
/SCLK (approx. 4.0 s)
Clock Period
Oscillation stabilization delay timer
for sub-clock
2
14
/SCLK (approx. 2.0 s)
Watchdog timer
2
10
/SCLK (approx. 125.0 ms)
2
13
/SCLK (approx. 1.0 s)
2
14
/SCLK (approx. 2.0 s)
2
16
/SCLK (approx. 4.0 s)
相關(guān)PDF資料
PDF描述
MB90F523BPFF Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-LCCC -55 to 125
MB90F523BPFV Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125
MB90V520 16-bit Proprietary Microcontroller
MB90522 36-Bit Bus Transceivers With 3-State Outputs 100-LQFP -55 to 125
MB90522PFF Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125
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