參數(shù)資料
型號(hào)： MB90F523B
廠商： Fujitsu Limited
英文描述： Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125
中文描述： 16位微控制器專有
文件頁(yè)數(shù)： 19/99頁(yè)
文件大?。?/td> 978K
代理商： MB90F523B
MB90520A/520B Series
19
Conditions when output from ports 0 and 1 is undefined
After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabili-
zation delay time controlled by the regulator circuit (during the power-on reset) . The figure below shows the
timing.
Note that this undefined output period does not occur on products without an internal regulator circuit as these
products do not have an oscillation stabilization delay time.
Note : See the “
I
PRODUCT LINEUP” section for details of which MB90520A/520B series products have an internal
regulator circuit.
Initialization
The device contains internal registers that are only initialized by a power-on reset. To initialize these registers,
restart the power supply.
Notes on using the DIV A
,
Ri and DIVW A
,
RWi instructions
Set the corresponding bank registers (DTB, ADB, USB, SSB) to “00
H
” when using the signed division instruc-
tions “DIV A, Ri” and “DIVW A, RWi”.
If the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00
H
”, the remainder value
produced by the instruction is not stored in the instruction operand register.
Notes on using REALOS
The extended intelligent I/O service (EI
2
OS) cannot be used when using REALOS.
Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
V
CC
(Power supply pin)
PONR (Power-on reset) signal
RST (External asynchronous reset) signal
RST (Internal reset) signal
Oscillation clock signal
KA (Internal operating clock A) signal
KB (Internal operating clock B) signal
PORT (port output) signal
Oscillation stabilization delay time
*2
Undefined output time
Regulator circuit stabilization
delay time
*1
*1 : Regulator circuit oscillation stabilization delay time : 2
17
/Oscillation clock frequency
(approx. 8.19 ms for a 16 MHz oscillation clock frequency)
*2 : Oscillation stabilization delay time : 2
18
/Oscillation clock frequency
(approx. 16.38 ms for a 16 MHz oscillation clock frequency)
Timing chart for undefined output from ports 0 and 1
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