參數(shù)資料
型號(hào): MB90F337PFM
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù): 58/92頁(yè)
文件大?。?/td> 858K
代理商: MB90F337PFM
MB90335 Series
61
17. Low power consumption (standby) mode
The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption
mode.
CPU operation mode and functional description
Register list
CPU
operating clock
Operation
mode
Description
PLL clock
Normal run
The CPU and peripheral resources operate at the clock frequency obtained by
PLL multiplication of oscillator clock (HCLK) frequency.
Sleep
Only peripheral resources operate at the clock frequency obtained by PLL
multiplication of the oscillator clock (HCLK) frequency.
Time-base
timer
Only the time-base timer operates at the clock frequency obtained by PLL
multiplication of the oscillator clock (HCLK) frequency.
Stop
The CPU and peripheral resources are suspended with the oscillator clock
stopped.
Main clock
Normal run
The CPU and peripheral resources operate at the clock frequency obtained by
dividing the oscillator clock (HCLK) frequency by two.
Sleep
Only peripheral resources operate at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Time-base
timer
Only the time-base timer operates at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Stop
The CPU and peripheral resources are suspended with the oscillator clock
stopped.
CPU intermittent
operation mode
Normal run
The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for
operation while being decimated in a certain period.
Low power consumption mode control register (LPMCR)
Initial Value
Address : 0000A0H
00011000B
( W )
( R/W )
( W )
( R/W )
76
5
4
3
21
0
SLP
( W )
STP
SPL
RST
TMD
CG1
CG0
Reserved
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