參數(shù)資料
型號(hào): MB90F337PFM
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 2/92頁
文件大小: 858K
代理商: MB90F337PFM
MB90335 Series
10
■ HANDLING DEVICES
1.
Preventing latch-up and turning on power supply
latch-up may occur on CMOS IC under the following conditions:
If a voltage higher than VCC or lower than VSS is applied to input and output pins.
A voltage higher than the rated voltage is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using CMOS IC, take great care to prevent the occurrence of latch-up.
2.
Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent dam-
age. Unused input pins should always be pulled up or down through resistance of at least 2 k
. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
3.
About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
4.
Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1
F between VCC and VSS pins
near this device.
5.
About crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
6.
Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
X0
X1
OPEN
Using external clock
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