參數(shù)資料
型號: MB90F337PFM
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 54/92頁
文件大小: 858K
代理商: MB90F337PFM
MB90335 Series
58
14. Address matching detection function
When the address is equal to the value set in the address detection register, the instruction code to be read into
the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9
instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the
program patch function is enabled.
2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address
matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code
to be read into the CPU is forcibly replaced with the INT9 instruction code.
Register list
Program address detect register 0 (PADR0)
Program address detect register 1 (PADR1)
Program address detect control status register (PACSR)
R/W : Readable and Writable
X
: Undefined
PADR0 (lower)
Initial Value
Address : 001FF0H
XXXXXXXXB
PADR0 (middle)
Initial Value
Address : 001FF1H
XXXXXXXXB
PADR0 (upper)
Initial Value
Address : 001FF2H
XXXXXXXXB
PADR1 (lower)
Initial Value
Address : 001FF3H
XXXXXXXXB
PADR1 (middle)
Initial Value
Address : 001FF4H
XXXXXXXXB
PADR1 (upper)
Initial Value
Address : 001FF5H
XXXXXXXXB
PACSR
Initial Value
Address : 00009EH
00000000B
(R/W)
76
5
4
3
2
1
0
(R/W)
15
14
13
12
11
10
9
8
(R/W)
76
5
4
3
2
1
0
(R/W)
15
14
13
12
11
10
9
8
(R/W)
76
5
4
3
2
1
0
(R/W)
15
14
13
12
11
10
9
8
(R/W)
76
5
4
3
2
1
0
(R/W)
AD1E
AD0E
Reserved Reserved Reserved Reserved
Reserved
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