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參數(shù)資料
| 型號(hào)： | MB90F244 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-CFP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 5/67頁(yè) |
| 文件大小： | 1403K |
| 代理商： | MB90F244 |
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5
MB90F244
I
PIN DESCRIPTION
Pin no.
TQFP-80*
62
63
39 to 41
Pin name
Circuit
type
Function
X0
X1
MD0 to MD2
A
Crystal oscillator pins (50 MHz)
C
Operating mode selection input pins
Connect directly to V
CC
5 or V
SS
. In the flash memory mode,
these pins are set to be V
ID
(= 12.0 V) input pins by performing
a proper operation.
External reset request input pin
Hardware standby input pin
General-purpose I/O port
I/O pins for the lower 8 bits of the external data bus
Data I/O pins for each operation command
This function is valid in the flash memory mode.
General-purpose I/O port
This function is valid when the external bus 8-bit mode.
I/O pins for the upper 8 bits of the external data bus
This function is valid when 16-bit bus mode.
Data I/O pins for each operation command
This function is valid in the flash memory mode.
General-purpose I/O port
Output pins for the medium 8 bits of the external address bus
Address input pins for each operation command
This function is valid in the flash memory mode.
General-purpose I/O port
This function is valid when the corresponding bit of the middle
address control register specification is “port”.
Output pins for the medium 8 bits of the external address bus
This function is valid when the corresponding bit of the middle
address control register specification is “port”.
Address input pins for each operation command
This function is valid in the flash memory mode.
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
External address bus output pin of the bit 16
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
Address input pin for each operation command
This function is valid in the flash memory mode.
60
42
RST
HST
P00 to P07
D00 to D07
DQ0 to DQ7
B
D
E
65 to 72
73 to 80
P10 to P17
E
D08 to D15
DQ8 to DQ15
1 to 8
P20 to P27
A00 to A07
AQ0 to AQ7
F
10 to 17
P30 to P37
F
A08 to A15
AQ8 to AQ15
18
P40
F
A16
AQ16
*: FPT-80P-M15
(Continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90F244PFT-G | Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-LCCC -55 to 125 |
| MB90F334A | 16-bit Proprietary Microcontroller |
| MB90F334APFF | 16-bit Proprietary Microcontroller |
| MB90F334APMC | 16-bit Proprietary Microcontroller |
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參數(shù)描述 |
|---|---|
| MB90F334APMC1-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC1-G-SPE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-SNE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-SPE1 | 制造商:FUJITSU 功能描述: |
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