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參數(shù)資料
| 型號： | MB81V4400C-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動態(tài)RAM) |
| 中文描述： | 100萬的CMOS × 4位快速頁面模式動態(tài)RAM的CMOS（100萬× 4位快速頁模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 302K |
| 代理商： | MB81V4400C-60 |
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21
MB81V4400C-60/MB81V4400C-70
HIGH-Z
Fig. 16 – TEST MODE SET CYCLE (A
0
to A
9
, OE = “H” or “L”)
DESCRIPTION
Test Mode ;
The purpose of this test mode is to reduce device test time to half of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of
CA0. In the write mode, data is written into eight cells simultaneously. But the data must be input from all DQ pins. In the read
mode, the data of eight cells at the selected addresses are read out from DQ and checked in the following manner
When the eight bits are all “L” or all “H”, a “H” level is output..
When the eight bits show a combination of “L” and “H”, a “L” level is output..
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 5ns from the specified value in the data sheet..
t
RC
, t
RWC
, t
RAC
, t
AA
, t
RAS
, t
CSH
, t
RAL
, t
RWD
, t
AWD
, t
PC
, t
PRWC
, t
CPA
, t
RHCP
, t
CPWD
“H” or “L”
t
RC
V
IH
V
IL
D
OUT
t
RP
t
RAS
t
CPN
t
CSR
t
CHR
t
RPC
t
WSR
t
WHR
t
OFF
t
OH
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
WE
CAS
RAS
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| MB81V4400C-70 | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動態(tài)RAM) |
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