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參數(shù)資料
| 型號： | MB81V4400C-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動態(tài)RAM) |
| 中文描述： | 100萬的CMOS × 4位快速頁面模式動態(tài)RAM的CMOS（100萬× 4位快速頁模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MB81V4400C-60 |
1
DS05-10174-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 1M
FAST PAGE MODE DYNAMIC RAM
×
4 BIT
MB81V4400C-60/-70
CMOS 1,048,576
×
4 BIT Fast Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V4400C is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory
cells accessible in 4-bit increments. The MB81V4400C features a “fast page” mode of operation whereby high-
speed random access of up to 1,024
×
4-bits of data within the same row can be selected. The MB81V4400C
DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB81V4400C is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB81V4400C is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and
extends the time interval between memory refreshes. Clock timing requirements for the MB81V4400C are not
critical and all inputs are LVTTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB81V4400C-60
60 ns max.
15 ns min.
30 ns max.
110 ns max.
40 ns min.
220 mW max.
7.2 mW max. (LVTTL level)/3.6 mW max. (CMOS level)
MB81V4400C-70
70 ns max.
20 ns min.
35 ns max.
125 ns max.
45 ns min.
195 mW max.
RAS Access Time
CAS Access Time
Address Access Time
Random Cycle Time
Fast Page Mode Cycle Time
Low power Dissipation
Operating current
Standby current
1,048,576 words
×
4 bit organization
Silicon gate, CMOS, 3D-Stacked Capacitor Cell
All input and output are LVTTL compatible
1024 refresh cycles every 16.4 ms
Self refresh function
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Fast page Mode, Read-Modify-Write Capability
On chip substrate bias generator for high
Performance
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
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