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參數(shù)資料
| 型號： | MB81V4405C-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 348K |
| 代理商： | MB81V4405C-70 |
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DS05-10185-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 1M
HYPER PAGE MODE DYNAMIC RAM
×
4 BIT
MB81V4405C-60/-70
CMOS 1,048,576
×
4 BIT Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V4405C is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory
cells accessible in 4-bit increments. The MB81V4405C features the “hyper page” mode of operation which
provides extended valid time for data output and higher speed random access of up to 1,024-bits of data within
the same row than the fast page mode. The MB81V4405C DRAM is ideally suited for mainframe, buffers, hand-
held computers video imaging equipment, and other memory applications where very low power dissipation and
high bandwidth are basic requirements of the design. Since the standby current of the MB81V4405C is very
small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or
auxiliary power.
The MB81V4405C is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and
extends the time interval between memory refreshes. Clock timing requirements for the MB81V4405C are not
critical and all inputs are LVTTL compatible.
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ABSOLUTE MAXIMUM RATINGS (See NOTE.)
NOTE:
Permanent device damage may occur if the above
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
are exceeded. Functional
Parameter
Symbol
Value
Unit
Voltage at any pin relative to V
SS
V
IN
, V
OUT
–0.5 to +4.6
V
Voltage of V
CC
supply relative to V
SS
V
CC
–0.5 to +4.6
V
Power Dissipation
P
D
1.0
W
Short Circuit Output Current
I
OUT
–50 to +50
mA
°
C
Storage Temperature
T
STG
–55 to +125
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
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