參數(shù)資料
型號(hào)： MB814100C-70
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 1位快速頁(yè)面模式的DRAM（的CMOS 4米× 1位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 273K
代理商： MB814100C-70
20
MB814100C-60/MB814100C-70
Fig. 16 – SELF REFRESH CYCLE (A
0
to A
10
= OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
Note . Assumes self refresh cycle only
Parameter
Unit
Min.
Max.
No.
Min.
Max.
100
—
100
100
Symbol
101
125
—
—
110
102
–50
–50
—
HIGH-Z
“H” or “L”
—
—
μ
s
ns
ns
RAS pulse Width
RAS precharge Time
CAS Hold Time
1024 times of burst refresh
Read/Write operation
1024 times of burst refresh
Self Refresh operation
Read/Write operation
MB814100C-60
MB814100C-70
V
IH
V
IL
t
CPN
RAS
t
CSR
t
RASS
t
RPS
t
RPC
t
CHS
t
WHR
t
WSR
t
OFF
t
OH
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
WE
D
OUT
t
RASS
t
RPS
t
CHS
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated
in the self refresh cycle and refresh operation can be autmatically executed using internal refresh address counter.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s), the
device can be entered the self refresh cycle. And after that, refresh operation is autmatically executed per fixed interval using internal refresh
address counter during “RAS = L” and “CAS = L”.
And exit from self refresh cycle is performed by toggling of RAS and CAS to “H” with specifying t
CHS
min.
Restruction for Self refresh operating;
For self refresh operation, the notice below must be considered.
1) In the case that distribute CBR refresh are operated in read/write cycles
Self refresh cycles can be executed without special rule if 1024 cycles of distribute CBR refresh are executed within t
REF
max..
2) In the case that burst CBR refresh or RAS only refresh are operated in read/write cycles
1024 times of burst CBR refresh or 1024 times of burst RAS only refresh must be executed before and after Self refresh cycles.
t
NS
< 1 ms
t
SN
< 1 ms
t
RASS
V
IH
V
IL
RAS
相關(guān)PDF資料
PDF描述
MB814100D-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
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