參數(shù)資料
型號(hào): MB814100C-70
廠商: Fujitsu Limited
英文描述: CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 的CMOS 4米× 1位快速頁(yè)面模式的DRAM(的CMOS 4米× 1位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 17/24頁(yè)
文件大?。?/td> 273K
代理商: MB814100C-70
17
MB814100C-60/MB81400C-70
Fig. 13 – HIDDEN REFRESH CYCLE
t
OH
t
WHR
t
CAC
t
ASR
t
WP
t
WHR
t
WSR
t
WSR
DESCRIPTION
The hidden refresh is executed by keeping CAS “L” to next cycle, i.e., the output data at previous cycle is kept during next refresh
cycle. Since the CAS is kept low continuously from previous cycle, followed refresh cycle should be CAS-before-RAS refresh.
WE must be held “H” for the specified set up time (t
WSR
) before RAS goes “L” for the secound time in order not to enter “test mode”
t
RAH
t
RP
“ H ” or “ L ”
VALID DATA
HIGH-Z
t
RC
t
RAS
t
RP
t
RC
t
RAS
t
CHR
t
RSH
t
RCD
t
RAD
t
ASC
t
RCS
t
RRH
t
RAL
t
CAH
COLUMN ADD.
ROW
ADDRESS
t
AA
t
RAC
t
OFF
t
OH
t
DH
t
DS
t
WP
t
AWD
t
RWD
t
CWD
t
CRP
t
RCS
t
WHR
t
WSR
t
WHR
t
ON
VALID DATA
HIGH-Z
VALID
t
RCS
t
OFF
t
ON
t
RAC
t
CAC
t
AA
t
WSR
t
CWD
t
AWD
t
RWD
t
RCS
t
DS
VALID
t
DH
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
A
0
to A
10
WE
(Read)
D
OUT
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
WE
(Read/Write
Cycle)
WE
(Read/Write
Cycle)
D
IN
WE
(Read)
D
OUT
D
IN
[Normal mode]
[Test mode]
相關(guān)PDF資料
PDF描述
MB814100D-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
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