參數資料
型號: MB814100C-70
廠商: Fujitsu Limited
英文描述: CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位快速頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 4米× 1位快速頁面模式的DRAM(的CMOS 4米× 1位快速頁面存取模式動態(tài)內存)
文件頁數: 11/24頁
文件大小: 273K
代理商: MB814100C-70
11
MB814100C-60/MB81400C-70
“H” or “L”
ROW ADD
VALID
DATA
HIGH-Z
Fig. 5 – READ CYCLE
COLUMN ADD
Invalid Data
HIGH-Z
DESCRIPTION
The read cycle is executed by keeping both RAS and CAS “L” and keeping WE “H” throughout the cycle. The row and column addresses
are latched with RAS and CAS, respectively. The data output remains valid with CAS “L”, ie., if CAS goes “H” , the data becomes invalid
after t
OH
is satisfied. The access time is determined by RAS (t
RAC
), CAS (t
CAC
), or Column address input (t
AA
). If t
RCD
(RAS to CAS delay
time) is greater than the specification, the access time is t
AA
.
t
RC
t
RCS
t
RAS
t
CRP
t
RCD
t
CSH
t
RP
t
RSH
t
CAS
t
RAH
t
ASC
t
RAD
t
ASR
RAS
t
CAH
t
CAL
t
RAL
t
OH
t
RCH
t
RRH
t
AA
t
RAC
t
OFF
t
CAC
t
ON
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
WE
D
OUT
A
0
to A
10
相關PDF資料
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