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參數(shù)資料
| 型號： | MB814100C-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 1位快速頁面模式的DRAM（的CMOS 4米× 1位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 273K |
| 代理商： | MB814100C-60 |
5
MB814100C-60/MB81400C-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
ADDRESS INPUTS
FUNCTIONAL OPERATION
Twenty-two input bits are required to decode any one of 4,194,304 cell addresses in the memory matrix. Since only
eleven address bits (A
0
- A
10
) are available, the column and row inputs are separately strobed by RAS and CAS as
shown in Figure 5. First, eleven row address bits are applied on pins A
strobe (RAS) then, eleven column address bits are applied and latched with the column address strobe (CAS). Both
row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address
latches are of the flow-through type; thus, address information appearing after t
RAH
(min)+ t
T
is automatically treated
as the column address.
0
-through-A
10
and latched with the row address
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of two basic ways--an early write cycle and a read-modify-write cycle.
The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the
input data is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS.
In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all
setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to
that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low.
When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max).
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max).
The data remains valid until either CAS returns to a High logic level. When an early write is executed, the output
buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode
is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these
conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast
page of memory, any of 2,048-bits can be accessed and, when multiple MB814100As are used, CAS is decoded
to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and
combinations of read, write, and/or ready-modify-write cycles are permitted.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp
Supply Voltage
V
CC
4.5
5.0
5.5
V
0
°
C to +70
°
C
V
SS
0
0
0
Input High Voltage, all inputs
V
IH
2.4
—
6.5
V
Input Low Voltage, all inputs*
V
IL
–0.3
—
0.8
V
1
1
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| MB81416-10 | 制造商:Fuji Electric 功能描述:81416-10/MB |
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| MB814400C-70PJN | 制造商:FUJITSU 功能描述:Dynamic RAM, Fast Page, 1M x 4, 26 Pin, Plastic, SOJ |
| MB814405D-60PJN | 制造商:FUJITSU Component Ltd 功能描述: |
| MB8146112 | 制造商:FUJITSU 功能描述:* |
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