參數(shù)資料
型號(hào)： MB8117405A-70
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（4米× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 348K
代理商： MB8117405A-70
25
MB8117405A-60/MB8117405A-70
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
CAS
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
—
—
55
50
(At recommended operating conditions unless otherwise noted.)
Symbol
35
—
—
ns
35
71
72
73
77
—
—
ns
70
99
—
—
ns
90
99
—
—
ns
90
MB8117405A-60
MB8117405A-70
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse width
RAS Hold Time
Note. Assumes that CAS-before-RAS refresh counter test cycle only..
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
10
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
WE
DQ
(Input)
OE
70
69
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
“H” or “L”
Valid Data out
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality
of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
10
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
10
are defined by latching levels on A
0
-A
10
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses generated by the internal
refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
t
FRSH
t
RP
t
CHR
t
CSR
t
CP
t
FCAS
t
FCAH
t
ASC
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
DZC
t
OED
t
FCAC
t
OEZ
t
ON
t
DZO
t
FCWD
t
OEA
相關(guān)PDF資料
PDF描述
MB8117405B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117405B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117800A-70 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117800A-60 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117805A-60 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB8117800A-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB812 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:*
MB812.833 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:*
MB-8120 制造商:Maxxtro 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*