參數(shù)資料
型號(hào)： MAX9877AERP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 0K
描述： IC SUBSYSTEM MONO AUD 20MAXFILM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： DirectDrive®
類(lèi)型： D 類(lèi)
輸出類(lèi)型： 1-通道（單聲道），帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 825mW x 1 @ 4 歐姆; 53mW x 2 @ 16 歐姆
電源電壓： 2.7 V ~ 5.25 V
特點(diǎn)： 消除爆音，I²C，輸入多路復(fù)用器，短路和熱保護(hù)，關(guān)機(jī)，音量控制
安裝類(lèi)型： 表面貼裝
供應(yīng)商設(shè)備封裝： 20-UCSP
封裝/外殼： 20-WFBGA，CSPBGA
包裝： 帶卷 (TR)
MAX9877AERP
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
16
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
A1
HPR
Right Headphone Output
A2
HPL
Left Headphone Output
A3
VSS
Headphone Amplifier Negative Power Supply. Bypass with a 1F capacitor to PGND.
A4
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1F capacitor between C1P and C1N.
A5
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1F capacitor between C1P and C1N.
B1
VDD
Analog Supply. Connect to PVDD. Bypass with a 1F capacitor to GND.
B2
BIAS
Common-Mode Bias. Bypass to GND with a 1F capacitor. Pulse low to reset the part and place in
shutdown (see the Typical Application Circuit).
B3
SDA
Serial-Data Input. Connect a pullup resistor from SDA to a 1.7V to 3.6V supply.
B4
RXIN+
Receiver Bypass Positive Input
B5
OUT+
Positive Speaker Output
C1
INB2
Input B2. Right input or positive input (see the Differential Input Configuration (
IN_) section).
C2
INB1
Input B1. Left input or negative input (see the Differential Input Configuration (
IN_) section).
C3
SCL
Serial-Clock Input. Connect a pullup resistor from SCL to a 1.7V to 3.6V supply.
C4
PGND
Power Ground
C5
PVDD
Class D and Charge-Pump Power Supply. Bypass with a 1F capacitor to PGND.
D1
INA2
Input A2. Right input or positive input (see the Differential Input Configuration (
IN_) section).
D2
INA1
Input A1. Left input or negative input (see the Differential Input Configuration (
IN_) section).
D3
GND
Analog Ground
D4
RXIN-
Receiver Bypass Negative Input
D5
OUT-
Negative Speaker Output
Detailed Description
Signal Path
The MAX9877A signal path consists of flexible inputs,
signal mixing, volume control, and output amplifiers
(Figure 1).
The inputs can be configured for single-ended or differ-
ential signals (Figure 2). The internal preamplifiers fea-
ture three programmable gain settings of 0dB, +9dB,
and +20dB. Following preamplification, the input sig-
nals are mixed, volume adjusted, and routed to the
headphone and speaker amplifiers based on the out-
put mode configuration (see Table 7). The volume con-
trol stages provide up to 75dB attenuation. The
headphone amplifier is configured as a unity-gain
buffer while the speaker amplifier provides +12dB of
additional gain.
When an input is configured as mono differential it can
be routed to the speaker or to both headphones. When
an input is stereo, it is mixed to mono without attenuation
for the speaker and kept stereo for the headphones.
When the application does not require the use of both
INA_ and INB_, the SNR of the MAX9877A is improved
by deselecting the unused input through the I2C output
mode register and AC-coupling the unused inputs to
ground with a 330pF capacitor. The 330pF capacitor
and the input resistance to the MAX9877A form a high-
pass filter preventing audible noise from coupling into
the outputs.
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