參數(shù)資料
型號： MAX9877AERP+T
廠商： Maxim Integrated Products
文件頁數(shù)： 18/31頁
文件大小： 0K
描述： IC SUBSYSTEM MONO AUD 20MAXFILM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： DirectDrive®
類型： D 類
輸出類型： 1-通道（單聲道），帶立體聲耳機
在某負(fù)載時最大輸出功率 x 通道數(shù)量： 825mW x 1 @ 4 歐姆; 53mW x 2 @ 16 歐姆
電源電壓： 2.7 V ~ 5.25 V
特點： 消除爆音，I²C，輸入多路復(fù)用器，短路和熱保護(hù)，關(guān)機，音量控制
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 20-UCSP
封裝/外殼： 20-WFBGA，CSPBGA
包裝： 帶卷 (TR)
MAX9877AERP
A
0
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE
ACKNOWLEDGE FROM MAX9877A
R/W
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9877A
B1
B0
B3
B2
B5
B4
B7
B6
S
A
P
Figure 9. Writing One Byte of Data to the MAX9877A
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 8. Acknowledge
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
______________________________________________________________________________________
25
Early STOP Conditions
The MAX9877A recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The MAX9877A is preprogrammed with a slave
address of 1001101R/(W). The address is defined as
the seven most significant bits (MSBs) followed by the
Read/Write bit. Setting the Read/Write bit to 1 config-
ures the MAX9877A for read mode. Setting the
Read/Write bit to 0 configures the MAX9877A for write
mode. The address is the first byte of information sent
to the MAX9877A after the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9877A uses to handshake receipt each byte of
data when in write mode (see Figure 8). The
MAX9877A pulls down SDA during the entire master-
generated 9th clock pulse if the previous byte is suc-
cessfully received. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master may retry communication.
The master pulls down SDA during the ninth clock
cycle to acknowledge receipt of data when the
MAX9877A is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9877A, fol-
lowed by a STOP condition.
Write Data Format
A write to the MAX9877A includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the MAX9877A.
Figure 10 illustrates the frame format for writing n-bytes
of data to the MAX9877A.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9877A.
The MAX9877A acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
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