I2C Register Description Zero-Crossing Detection (ZCD) Zero-crossing" />
參數(shù)資料
型號： MAX9877AERP+T
廠商： Maxim Integrated Products
文件頁數(shù)： 14/31頁
文件大?。?/td> 0K
描述： IC SUBSYSTEM MONO AUD 20MAXFILM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： DirectDrive®
類型： D 類
輸出類型： 1-通道（單聲道），帶立體聲耳機(jī)
在某負(fù)載時最大輸出功率 x 通道數(shù)量： 825mW x 1 @ 4 歐姆; 53mW x 2 @ 16 歐姆
電源電壓： 2.7 V ~ 5.25 V
特點(diǎn)： 消除爆音，I²C，輸入多路復(fù)用器，短路和熱保護(hù)，關(guān)機(jī)，音量控制
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 20-UCSP
封裝/外殼： 20-WFBGA，CSPBGA
包裝： 帶卷 (TR)
MAX9877AERP
I2C Register Description
Zero-Crossing Detection (ZCD)
Zero-crossing detection limits distortion in the output
signal during volume transitions by delaying the transi-
tion until the mixer output crosses the internal bias volt-
age. A timeout period (typically 60ms) forces the
volume transition if the mixer output signal does not
cross the bias voltage.
1 = Zero-crossing detection is enabled.
0 = Zero-crossing detection is disabled.
Differential Input Configuration (
IN_)
The inputs INA_ and INB_ can be configured for mono
differential or stereo single-ended operation.
1 = IN_ is configured as a mono differential input with
IN_2 as the positive and IN_1 as the negative input.
0 = IN_ is configured as a stereo single-ended input
with IN_2 as the right and IN_1 as the left input.
Preamplifier Gain (PGAIN_)
The preamplifier gain of INA_ and INB_ can be pro-
grammed by writing to PGAIN_.
00 = 0dB
01 = +9dB
10 = +20dB
11 = Reserved
The MAX9877A is controlled through five I2C program-
mable registers. Table 1 shows the MAX9877A’s com-
plete register map. Tables 2, 3, and 5 show the
individual registers.
I2C Address
The slave address of the MAX9877A is 1001101R/(W).
Table 1. Register Map
REGISTER
ADDRESS
POR STATE
B7
B6
B5
B4
B3
B2
B1
B0
Input Mode
Control
0x00
0x40
0
ZCD
INA
INB
PGAINA
PGAINB
Speaker
Volume
Control
0x01
0x00
0
SVOL (Table 4)
Left
Headphone
Volume
Control
0x02
0x00
0
HPLVOL (Table 4)
Right
Headphone
Volume
Control
0x03
0x00
0
HPRVOL (Table 4)
Output Mode
Control
0x04
0x49
SHDN
BYPASS
OSC (Table 6)
OUTMODE (Table 7)
Table 2. Input Mode Control
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0
ZCD
INA
INB
PGAINA
PGAINB
I2C Interface
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
______________________________________________________________________________________
21
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