參數(shù)資料
型號： MAX9877AERP+T
廠商： Maxim Integrated Products
文件頁數(shù)： 28/31頁
文件大?。?/td> 0K
描述： IC SUBSYSTEM MONO AUD 20MAXFILM
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
系列： DirectDrive®
類型： D 類
輸出類型： 1-通道（單聲道），帶立體聲耳機
在某負載時最大輸出功率 x 通道數(shù)量： 825mW x 1 @ 4 歐姆; 53mW x 2 @ 16 歐姆
電源電壓： 2.7 V ~ 5.25 V
特點： 消除爆音，I²C，輸入多路復用器，短路和熱保護，關(guān)機，音量控制
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 20-UCSP
封裝/外殼： 20-WFBGA，CSPBGA
包裝： 帶卷 (TR)
MAX9877AERP
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0,
SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND.
SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2-WIRE INTERFACE TIMING
External Pullup Voltage Range:
SDA and SCL
1.7
3.6
V
Serial Clock Frequency
fSCL
DC
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
START Condition Hold
tHD:STA
0.6
s
START Condition Setup Time
tSU:STA
0.6
s
Clock Low Period
tLOW
1.3
s
Clock High Period
tHIGH
0.6
s
Data Setup Time
tSU:DAT
100
ns
Data Hold Time
tHD:DAT
0
900
ns
Maximum Receive SCL/SDA Rise
Time
tR
300
ns
Maximum Receive SCL/SDA Fall
Time
tF
300
ns
Setup Time for STOP Condition
tSU:STO
0.6
s
Capacitive Load for Each Bus
Line
Cb
400
pF
Note 3: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.
Note 4: Amplifier inputs are AC-coupled to GND.
Note 5: Output levels higher than 825mW are not recommended for extended durations. Production tested with ZSPK = 8 + 68H only.
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