SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 49 Maxim Integrated
參數(shù)資料
型號(hào)： MAX3108EWA+T
廠商： Maxim Integrated Products
文件頁數(shù)： 44/56頁
文件大小： 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
49
Maxim Integrated
I2C Interface
The MAX3108 contains an I2C-compatible interface for
data communication with a host processor (SCL and
SDA). The interface supports a clock frequency of up
to 1MHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
START, STOP, and Repeated START Conditions
When writing to the MAX3108 using I2C, the master
sends a START condition (S) followed by the MAX3108
I2C address. After the address, the master sends
the register address of the register that is to be pro-
grammed. The master then ends communication by
issuing a STOP condition (P) to relinquish control of the
bus, or a repeated START condition (Sr) to communicate
to another I2C slave. See Figure 17.
Slave Address
The MAX3108 includes a configurable 7-bit I2C slave
address, allowing up to 16 MAX3108 devices to share
the same I2C bus. The address is defined by connect-
ing the MOSI/A1 and CS/A0 inputs to DGND, VL, SCL,
or SDA (Table 5). Set the R/W bit high to configure the
MAX3108 to read mode. Set the R/W bit low to config-
ure the MAX3108 to write mode. The address is the
first byte of information sent to the MAX3108 after the
START condition.
Bit Transfer
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes
in SDA while SCL is high and stable are considered
control signals (see the START, STOP, and Repeated
START Conditions section). Both SDA and SCL remain
high when the bus is not active.
Figure 17. I2C START, STOP, and Repeated START Conditions
Table 5. I2C Address Map
SCL
SDA
SSrP
MOSI/A1
CS/A0
I2C WRITE
ADDRESS
I2C READ
ADDRESS
DGND
0xD8
0xD9
DGND
VL
0xC2
0xC3
DGND
SCL
0xC4
0xC5
DGND
SDA
0xC6
0xC7
VL
DGND
0xC8
0xC9
VL
0xCA
0xCB
VL
SCL
0xCC
0xCD
VL
SDA
0xCE
0xCF
SCL
DGND
0xD0
0xD1
SCL
VL
0xD2
0xD3
SCL
0xD4
0xD5
SCL
SDA
0xD6
0xD7
SDA
DGND
0xC0
0xC1
SDA
VL
0xDA
0xDB
SDA
SCL
0xDC
0xDD
SDA
0xDE
0xDF
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