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參數(shù)資料
| 型號： | MAX3108EWA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
19
Maxim Integrated
2x and 4x Rate Modes
The MAX3108 offers 2x and 4x rate modes in order to
support higher baud rates than possible with standard
operation using 16x sampling. In these modes, the refer-
ence clock rate only needs to be either 8x or 4x higher
than the baud rate, respectively. In 4x rate mode, each
received bit is only sampled once at the midbit instant
instead of the usual three samples to determine the
logic value of the received bit. This reduces the abil-
ity to detect line noise on the received data in 4x rate
mode. The 2x and 4x rate modes are selectable through
BRGConfig[5:4]. Note that IrDA encoding and decoding
does not operate in 2x and 4x rate modes.
When 2x rate mode is selected, the actual baud rate is
twice the rate programmed into the baud-rate genera-
tor. If 4x rate mode is enabled, the actual baud rate on
the line is quadruple that of the programmed baud rate
(Figure 8).
Multidrop Mode
In multidrop mode, also known as 9-bit mode, the data
word length is 8 bits and a 9th bit is used for distin-
guishing between an address word and a data word.
Multidrop mode is enabled by the MODE2[6]: MultiDrop
bit. The MultiDrop bit takes the place of the parity bit in
the data word structure. Parity checking is disabled and
an interrupt is generated in SpclCharInt[5]: MultiDropInt
when an address (9th bit is 1) is received while in multi-
drop mode.
It is up to the host processor to filter out the data intended
for its address. Alternatively, the auto data-filtering fea-
ture can be used to automatically filter out the data not
intended for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop Mode
In multidrop mode, the MAX3108 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
value and GPIO hardware inputs. Use either the entire
XOFF2 register or the XOFF2[7:4] bits in combination
with GPIO_ inputs to define the address.
Enable multidrop mode by setting the MODE2[6]:
MultiDrop bit high and enable auto data filtering by set-
ting the MODE2[4]: SpecialChr bit high.
When using register bits in combination with GPIO_
inputs to define the address, the MSB of the address
is written to the XOFF2[7:4] bits, while the LSBs of
the address are defined by the GPIOs. To enable this
address-definition method along with auto data filter-
ing, set the FlowCtrl[2]: GPIAddr bit high in addition to
the MODE2[4]: SpecialChr and MODE2[6]: MultiDrop
bits. The GPIO_ inputs are automatically read when the
FlowCtrl[2]: GPIAddr bit is set high, and the address
is automatically updated on logic changes to any GPIO
pin.
When using auto data filtering, the MAX3108 checks
each received address against the programmed station
address. When an address is received that matches
the station’s address, received data is stored in the
RxFIFO. When an address is received that does not
match the station’s address, received data is discarded.
Addresses are not stored into the FIFO but an inter-
rupt is still generated in SpclCharInt[5]: MultiDropInt
upon receiving an address. An additional interrupt is
generated in SpclCharInt[3]: XOFF2Int when the station
address is received.
Figure 8. 2x and 4x Baud Rates
FRACTIONAL
RATE
GENERATOR
fREF
BAUD RATE
BRGConfig[5:4]
DIV[LSB]
DIV[MSB]
NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.
FRACT
1x, 2x, 4x RATE
MODES
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