SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 48 Maxim Integrated Serial Contr" />
參數(shù)資料
型號(hào): MAX3108EWA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 43/56頁(yè)
文件大?。?/td> 0K
描述: IC UART
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
48
Maxim Integrated
Serial Controller Interface
The MAX3108 can be controlled through I2C or SPI
as defined by the logic on SPI/I2C. See the Bump
Configuration for further details.
SPI Interface
The SPI supports both single-cycle and burst read/write
access. The SPI master must generate clock and data
signals in SPI MODE0 (i.e., with clock polarity CPOL = 0
and clock phase CPHA = 0).
SPI Single-Cycle Access
Figure 15 shows a single-cycle read, and Figure 16
shows a single-cycle write.
SPI Burst Access
Burst access allows writing and reading multiple data
bytes in one block by defining only the initial register
address in the SPI command byte. Multiple characters
can be loaded into the TxFIFO by using the THR (0x00)
as the initial burst write address. Similarly, multiple
characters can be read out of the RxFIFO by using the
RHR (0x00) as the SPI’s burst read address. If the SPI
burst address is different from 0x00, the MAX3108 auto-
matically increments the register address after each SPI
data byte. Efficient programming of multiple consecutive
registers is thus possible. The chip-select input, CS/A0,
must be held low during the whole cycle. The SCLK/SCL
clock continues clocking throughout the burst access
cycle. The burst cycle ends when the SPI master pulls
CS/A0 high.
For example, writing 128 bytes into the TxFIFO can be
achieved by a burst write access using the following
sequence:
1) Pull CS/A0 low.
2) Send SPI write command to address 0x00.
3) Send 128 bytes.
4) Release CS/A0.
This takes a total of (1 + 128) x 8 clock cycles.
Figure 15. Single-Cycle Read
Figure 16. Single-Cycle Write
CS
RA6A5A4A3A2A1A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
MOSI
MISO
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS
CS
WA6A5A4A3A2A1A0D7D6D5D4D3D2D1D0
SCLK
MOSI
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS
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