參數(shù)資料
型號: MAX2101CMQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 消費家電
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: METRIC, QFP-100
文件頁數(shù): 8/24頁
文件大小: 217K
代理商: MAX2101CMQ
M
6-Bit Quadrature Digitizer
8
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
NAME
FUNCTION
1, 9,
12, 13,
18, 19,
63, 67,
82, 83,
89, 92,
98, 99
2
GND
Ground
VGNDQ
Q Channel Baseband Ground
PIN
3
BBINQ
Q Channel Baseband Amplifier,
External Input
4
FTUNEQ
Q Channel Filter Cutoff
Frequency Control
8
VCCQ
VGNDP
Q Channel Baseband +5V Supply
Prescaler Ground
7
BBOUTQB
Q Channel Baseband Amplifier
Inverted Output
6
BBOUTQ
Q Channel Baseband Amplifier
Output
5
OFFQ
Q Channel Baseband Amplifier
Offset Adjust
11
14
15
16
17
VCCP
TNKB
VCC2
VGND2
TNKA
VGNDAD
VSUBAD
Prescaler +5V Supply
Oscillator Resonator Port
Oscillator +5V Supply
Oscillator Ground
Oscillator Resonator Port
A/D Converter Ground
A/D Converter Substrate
10
20, 21
22, 59
26
27
28
VGNDO
D5Q
D4Q
Digital Output Ground
Q Channel Data Output, bit 5 (MSB)
Q Channel Data Output, bit 4
25, 29,
38, 40,
44, 52
VCCO
Digital Output +5V Supply
24
VCOPREB
Divide-by-16 Prescaler
Complementary Output
23
VCOPRE
Divide-by-16 Prescaler Output
30, 37,
43, 51,
55
31
VGNDO
Digital Output Ground
34, 47
VGNDD
Digital Logic Ground
33, 48
VCCD
Digital Logic +5V Supply
32
D2Q
Q Channel Data Output, bit 2
D3Q
Q Channel Data Output, bit 3
NAME
D1Q
D0Q
FUNCTION
35
36
Q Channel Data Output, bit 1
Q Channel Data Output, bit 0 (LSB)
PIN
42
45
46
49
DCLK
D0I
D1I
D2I
Data Clock Output
I Channel Data Output, bit 0 (LSB)
I Channel Data Output, bit 1
I Channel Data Output, bit 2
41
DCLKB
Data Clock Complementary Output
39
RCLK
Reference Clock, divide by six from
master clock (MCLK)
50
53
D3I
D4I
I Channel Data Output, bit 3
I Channel Data Output, bit 4
54
56
D5I
BINEN
I Channel Data Output, bit 5 (MSB)
Binary Enable
57
S2
Programmable Sample Rate
Control Input, bit 2 (MSB)
58
S1
Programmable Sample Rate
Control Input, bit 1
62
S0
Programmable Sample Rate
Control Input, bit 0 (LSB)
60, 61
VCCAD
A/D Converter +5V Supply
64
65
VCCC
MCLK
Clock Buffer +5V Supply
Master Clock
68
ENOPB
Offset Correction/Enable Correction
66
VGNDC
Clock Buffer Ground
69
CQB
Inverting Input Q Channel Offset
Correction
70
CQ
Noninverting Input Q Channel
Offset Correction
71
CI
Noninverting Input I Channel Offset
Correction
72
CIB
Noninverting Input I Channel Offset
Correction
73
VCCI
I Channel Baseband +5V Supply
74
BBOUTIB
I Channel Baseband Amplifier
Inverted Output
75
BBOUTI
I Channel Baseband Amplifier Output
76
OFFI
I Channel Baseband Amplifier
Offset Adjust
77
FTUNEI
I Channel Filter Cutoff Frequency
Control
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