參數(shù)資料
型號(hào): MAX2101CMQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 消費(fèi)家電
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: METRIC, QFP-100
文件頁(yè)數(shù): 16/24頁(yè)
文件大?。?/td> 217K
代理商: MAX2101CMQ
M
Digital S ignal Interfac ing
The single-ended, LS-TTL compatible data outputs
from the ADCs are clocked out with respect to the ris-
ing edge of the data clock (DCLK). The output drivers
provide sufficient logic levels at speeds up to 60Mbps
into a fanout of 1 with a total load capacitance of 15pF.
All data outputs should have approximately equivalent
loading to ensure proper setup and hold timing.
The data clock outputs are also LS-TTL compatible and
provide a signal to latch the data at rates up to
60Mbps. The outputs are differential to minimize the
harmonic energy that might feed back into the LO or IF
inputs. The balanced outputs should have equivalent
termination to minimize unwanted EMI.
Select either binary or twos-complement output with the
binary enable (BINEN) pin. A logic high will select offset
binary, and a logic low will select a twos-complement
format.
Input T ermination Network
The MAX2101 accepts as an input a narrow band IF
whose center frequency is located somewhere in the UHF
range, between 400MHz and 700MHz. The MAX2101
comprises a significant part of a receiver chain character-
ized by extremely high dynamic range coupled with
demanding intermodulation requirements. As such, it is
imperative to provide proper input termination to the
MAX2101, to minimize effective VSWR and noise figure at
this stage of the system RF signal processing chain.
The input of the MAX2101 is designed to deliver a
VSWR less than 2:1 over the 400MHz to 700MHz range.
The equivalent input network of the input pins IFIN and
IFINB is discussed and illustrated below. However,
standard narrow-band impedance matching tech-
niques can be used to improve on this VSWR for the
intended IF of the system.
Equivalent Input Circuitry
The MAX2101’s input amplifier is designed to provide a
controlled input impedance, provide gain for the signal
path, and provide for the component’s minimum noise
figure. The amplifier uses a feedback topology to pro-
vide gain that is insensitive to input frequency, in addi-
tion to delivering constant input impedance. Figure 12
illustrates the amplifier’s input portion.
Ideally, the input amplifier will be designed to match to
an anticipated source impedance of 50
. The resistive
portion of the input impedance at pin IFIN can be
approximated as follows:
R
(1 A )
where r
E
is the dynamic resistance at Q3’s emitter, and
A
V
is the open-loop gain of the differential-pair amplifier
stage.
The amplifier can be designed so the frequency
response does not appreciably affect the input imped-
ance. Details of the amplifier are left out for simplicity.
Figure 12 shows how several parasitic elements con-
tribute to the input impedance over the frequencies of
interest. C
PAD
represents the parasitic capacitance
associated with the bond pad and input metallization.
R
r
IN
F
E
=
+
6-Bit Quadrature Digitizer
16
______________________________________________________________________________________
150k
150k
150k
150k
71
75
74
BBOUTI
BBOUTIB
OFFI
ENOPB
OFFQ
72
76
68
CIB
CI
70
7
6
BBOUTQB
BBOUTQ
69
CQB
CQ
5
MAX2101
76
220nF
220nF
220nF
220nF
72
71
70
69
68
OFFI
OFFQ
CIB
CI
CQ
CQB
ENOPB
5
MAX2101
Figure 10. Offset Correction Network
Figure 11. Offset Correction
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