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參數(shù)資料
| 型號： | MAX2101CMQ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MAX2101CMQ |
M
6-Bit Quadrature Digitizer
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 4.75V to 5.25V, T
A
= +25°C, unless otherwise noted.)
R
L
= 50
external, f = 5MHz
V
OBB
= 0V
p-p
V
OBB
> 2V DC
R
L
= 1M
, C
L
= 15pF, V
O
= 0.5V
R
L
= 1M
, C
L
= 15pF, V
O
= 2.4V
R
L
= 1M
, C
L
= 15pF
R
L
= 1M
, C
L
= 15pF
R
L
= 1M
, C
L
= 15pF, V
O
= 0.5V
R
L
= 1M
, C
L
= 15pF, V
O
= 2.4V
R
L
= 1k
, C
L
= 0.1μF
R
L
= 1M
, C
L
= 15pF
R
L
= 1M
, C
L
= 15pF
LSB = 24mV, either channel
CONDITIONS
pF
V
5
C
IMCLK
V
OH
Master Clock Input Capacitance
Reference Clock Output High (Note 3)
k
2
R
IMCLK
Master Clock Input Resistance
dBm
0
10
P
MCLK
Master Clock Input Dynamic Range
μA
50
I
OL
Data Clock Output Sink Current
μA
400
I
OH
Data Clock Output Source Current (Note 3)
V
0.5
V
OL
Data Clock Output Low
V
2.2
V
OH
Data Clock Output High (Note 3)
μA
50
I
OL
Data Output Sink Current
μA
400
I
OH
Data Output Source Current (Note 3)
V
0.5
V
OL
Data Output Low
V
2.2
V
OH
Data Output High (Note 3)
V
V
1.5
V
PWR
V
PWR
LSB
A
VM
Power Detect Output Minimum
Power Detect Output Maximum
ADC LSB Size
ADC Amplitude Response Match
V
1.18
1.25
V
REF
Buffered Reference Voltage
(Zero Temperature Coefficient)
LSB
dB
1.0
INL
A
VRF
ADC Integral Nonlinearity
RF Signal Path DC Gain
LSB
1.0
DNL
ADC Differential Nonlinearity
LSB
0.5
V
OFFAD
ADC Input Offset
3.75
21
mV
dB
25
0.4
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
V
V
PTAT
Buffered Reference Voltage
(Proportional to Absolute Temperature)
R
L
= 1M
, C
L
= 15pF, V
O
= 2.4V
R
L
= 10M
, C
L
= 15pF
R
L
= 10M
, C
L
= 15pF
μA
400
I
OH
Reference Clock Output Source Current
(Note 3)
V
0.5
V
OL
Reference Clock Output Low
2.2
R
L
= 1M
, C
L
= 15pF, V
O
= 0.5V
μA
V
V
μA
μA
μA
μA
50
I
OL
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
Reference Clock Output Sink Current
Digital Input High Threshold (Note 5)
Digital Input Low Threshold (Note 5)
Digital Input Current High (Note 5)
Digital Input Current Low (Note 5)
FLTRSEL Input Current High
FLTRSEL Input Current Low
Channel to channel
AGC set to maximum gain
63
Entire signal path, DC,
V
FTUNEI
= V
FTUNEQ
= V
2R5
dB
0.5
M
(IQ)
Composite I/Q Gain Mismatch
2.0
0.8
-150
-400
V
IH
= 2.0V
V
IL
= 0.8V
V
IH
= 2.0V
V
IL
= 0.8V
-500
-790
V
PTAT
Temperature Coefficient
Buffered Reference Voltage
(2 x VREF)
R
L
= 40k
,
C
L
= 0.01μF
T
A
= 0°C to +70°C
mV/°C
4.5
T
A
= 0°C to +70°C
(Note 2)
T
A
= +25°C
1.0
1.3
0.9
1.5
Ratio of V
2R5
to V
REF
1.9
2.1
V
2R5
V
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