參數(shù)資料
型號(hào)： MA330013
廠商： Microchip Technology
文件頁數(shù)： 92/199頁
文件大?。?/td> 0K
描述： MODULE PLUG-IN DSPIC33 100TQFP
標(biāo)準(zhǔn)包裝： 1
附件類型： 插拔式模塊（PIM）- dsPIC33FJ256MC710
適用于相關(guān)產(chǎn)品： Explorer 16（DM240001 或 DM240002）
產(chǎn)品目錄頁面： 658 (CN2011-ZH PDF)
配用： DM330023-ND - BOARD DEV DSPICDEM MCHV
相關(guān)產(chǎn)品： DSPIC33FJ64MC710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC510T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC510T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ256MC510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ256MC510T-I/PF-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ128MC710T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC510T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC510T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
更多...
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2007 Microchip Technology Inc.
Preliminary
DS70165E-page 179
dsPIC33F
15.4
Center-Aligned PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in an
Up/Down Count mode (see Figure 15-3).
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3:
CENTER-ALIGNED PWM
15.5
PWM Duty Cycle Comparison
Units
There are four 16-bit Special Function Registers
(PDC1, PDC2, PDC3 and PDC4) used to specify duty
cycle values for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16 bits wide. The
LSb of a Duty Cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1
DUTY CYCLE REGISTER BUFFERS
The four PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle, there is a Duty Cycle
register that is accessible by the user and a second
Duty Cycle register that holds the actual compare value
used in the present PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER
register occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Count
mode, new duty cycle values are updated when the
value of the PTMR register is zero, and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Count
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
15.5.2
DUTY CYCLE IMMEDIATE UPDATES
When the Immediate Update Enable bit is set (IUE = 1),
any write to the Duty Cycle registers will update the
new duty cycle value immediately. This feature gives
the option to the user to allow immediate updates of the
active PWM Duty Cycle registers instead of waiting for
the end of the current time base period. System stabil-
ity is improved in closed-loop servo applications by
reducing the delay between system observation and
the issuance of system corrective commands when
immediate updates are enabled (IUE = 1).
If the PWM output is active at the time the new duty
cycle is written and the new duty cycle is less than the
current time base value, the PWM pulse width will be
shortened. If the PWM output is active at the time the
new duty cycle is written and the new duty cycle is
greater than the current time base value, the PWM
pulse width will be lengthened.
If the PWM output is inactive at the time the new duty
cycle is written and the new duty cycle is greater than
the current time base value, the PWM output will
become active immediately and will remain active for
the new written duty cycle value.
0
PTPER
PTMR
Value
Period
Period/2
Duty
Cycle
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