參數(shù)資料
型號(hào)： MA330013
廠商： Microchip Technology
文件頁數(shù)： 71/199頁
文件大?。?/td> 0K
描述： MODULE PLUG-IN DSPIC33 100TQFP
標(biāo)準(zhǔn)包裝： 1
附件類型： 插拔式模塊（PIM）- dsPIC33FJ256MC710
適用于相關(guān)產(chǎn)品： Explorer 16（DM240001 或 DM240002）
產(chǎn)品目錄頁面： 658 (CN2011-ZH PDF)
配用： DM330023-ND - BOARD DEV DSPICDEM MCHV
相關(guān)產(chǎn)品： DSPIC33FJ64MC710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC510T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64MC510T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ256MC510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ256MC510T-I/PF-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ128MC710T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC510T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128MC510T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
更多...
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dsPIC33F
DS70165E-page 160
Preliminary
2007 Microchip Technology Inc.
10.2
Open-Drain Configuration
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired digi-
tal only pins by using external pull-up resistors. (The
open-drain I/O feature is not supported on pins which
have analog functionality multiplexed on the pin.) The
maximum open-drain voltage allowed is the same as
the maximum VIH specification. The open-drain output
feature is supported for both port pin and peripheral
configurations.
10.3
Configuring Analog Port Pins
The use of the ADxPCFGH, ADxPCFGL and TRIS
registers control the operation of the ADC port pins.
The port pins that are desired as analog inputs must
have their corresponding TRIS bit set (input). If the
TRIS bit is cleared (output), the digital output level (VOH
or VOL) is converted.
Clearing any bit in the ADxPCFGH or ADxPCFGL reg-
ister configures the corresponding bit to be an analog
pin. This is also the Reset state of any I/O pin that has
an analog (ANx) function associated with it.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.4
I/O Port Write/Read Timing
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
10.5
Input Change Notification
The input change notification function of the I/O ports
allows the dsPIC33F devices to generate interrupt
requests
to
the
processor
in
response
to
a
change-of-state on selected input pins. This feature is
capable of detecting input change-of-states even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, there are up to 24 external sig-
nals (CN0 through CN23) that can be selected
(enabled) for generating an interrupt request on a
change-of-state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
CN interrupt enable (CNxIE) control bits for each of the
CN input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the weak pull-up
enable (CNxPUE) bits for each of the CN pins. Setting
any of the control bits enables the weak pull-ups for the
corresponding pins.
EXAMPLE 10-1:
PORT WRITE/READ EXAMPLE
Note:
In devices with two ADC modules, if the
corresponding
PCFG
bit
in
either
AD1PCFGH(L) and AD2PCFGH(L) is
cleared, the pin is configured as an analog
input.
Note:
The voltage on an analog input pin can be
between -0.3V to (VDD + 0.3 V).
Note:
Pull-ups
on
change
notification
pins
should always be disabled whenever the
port pin is configured as a digital output.
MOV
0xFF00, W0
; Configure PORTB<15:8> as inputs
MOV
W0, TRISBB
; and PORTB<7:0> as outputs
NOP
; Delay 1 cycle
btss
PORTB, #13
; Next Instruction
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