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| 型號： | MA330013 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 69/199頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE PLUG-IN DSPIC33 100TQFP |
| 標準包裝： | 1 |
| 附件類型： | 插拔式模塊（PIM）- dsPIC33FJ256MC710 |
| 適用于相關產(chǎn)品： | Explorer 16（DM240001 或 DM240002） |
| 產(chǎn)品目錄頁面： | 658 (CN2011-ZH PDF) |
| 配用： | DM330023-ND - BOARD DEV DSPICDEM MCHV |
| 相關產(chǎn)品： | DSPIC33FJ64MC710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64MC710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64MC510T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64MC510T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ256MC510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP DSPIC33FJ256MC510T-I/PF-ND - IC DSPIC MCU/DSP 256K 100TQFP DSPIC33FJ128MC710T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP DSPIC33FJ128MC710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP DSPIC33FJ128MC510T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP DSPIC33FJ128MC510T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP 更多... |
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dsPIC33F
DS70165E-page 158
Preliminary
2007 Microchip Technology Inc.
9.2.2
IDLE MODE
Idle mode has these features:
The CPU stops executing instructions.
The WDT is automatically cleared.
The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
Any interrupt that is individually enabled.
Any device Reset.
A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction, or
the first instruction in the ISR.
9.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV
instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
9.3
Doze Mode
Generally, changing clock speed and invoking one of the
power-saving modes are the preferred strategies for
reducing power consumption. There may be cir-
cumstances, however, where this is not practical. For
example, it may be necessary for an application to main-
tain uninterrupted synchronous communication, even
while it is doing nothing else. Reducing system clock
speed may introduce communication errors, while using
a power-saving mode may stop communications
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>).
There
are
eight
possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
It is also possible to use Doze mode to selectively
reduce power consumption in event-driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
9.4
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled via the appropriate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is only enabled if both the associ-
ated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC DSC variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MA330014 | 功能描述:子卡和OEM板 dsPIC33 MC RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330015 | 功能描述:子卡和OEM板 dsPIC33 GP RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330016 | 功能描述:子卡和OEM板 dsPIC33F GP RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330017 | 功能描述:子卡和OEM板 dsPIC33F MC RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330018 | 功能描述:子卡和OEM板 44P QFN TO 100P PIM dsPIC33FJ128MC804 RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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