參數(shù)資料
型號: M8813F3Y-90T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 61/85頁
文件大小: 601K
代理商: M8813F3Y-90T1
M88 FAMILY
64/85
Table 48A. CPLD Macrocell Asynchronou s Clock Mode Timing (5 V Range)
Table 48B. CPLD Macrocell Asynchronou s Clock Mode Timing (3 V Range)
Symbol
Parameter
Conditions
-90
-15
PT
Aloc
TURBO
OFF
Slew
Rate
Unit
Min
Max
Min
Max
fMAXA
Maximum Frequency
External Feedback
1/(tSA+tCOA)
26.32
21.27
MHz
Maximum Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10)
35.71
27.78
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
41.67
35.71
MHz
tSA
Input Setup Time
8
12
Add 2
Add 10
ns
tHA
Input Hold Time
12
14
ns
tCHA
Clock Input High
Time
12
15
Add 10
ns
tCLA
Clock Input Low
Time
12
15
Add 10
ns
tCOA
Clock to Output
Delay
30
37
Add 10
Sub 2
ns
tARDA
CPLD Array Delay
Any Macrocell
16
22
Add 2
ns
tMINA
Minimum Clock
Period
1/fCNTA
28
43
ns
Symbol
Parameter
Conditio ns
-15
PT
Aloc
TURBO
OFF
Slew
Rate
Unit
Min
Max
fMAXA
Maximum Frequency
External Feedback
1/(tSA+tCOA)
16.9
MHz
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
20.4
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
27
MHz
tSA
Input Setup Time
12
Add 4
Add 20
ns
tHA
Input Hold Time
15
ns
tCHA
Clock High Time
22
Add 20
ns
tCLA
Clock Low Time
15
Add 20
ns
tCOA
Clock to Output Delay
47
Add 20
Sub 6
ns
tARD
CPLD Array Delay
Any Macrocell
29
Add 4
ns
tMINA
Minimum Clock Period
1/fCNTA
43
ns
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