參數(shù)資料
型號(hào): M8813F3Y-90T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁(yè)數(shù): 39/85頁(yè)
文件大小: 601K
代理商: M8813F3Y-90T1
M88 FAMILY
44/85
Figu re 29. Port A and Port B Structure
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT
A OR B PIN
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8 ]
AI02887
Direction Register
The Direction Register, in conjunction with the
output enable (except for Port D), controls the
direction of data flow in the I/O Ports. Any bit set to
‘1’ in the Direction Register will cause the
corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode
for all port pins is input.
Figure
29
and
Figure
31
show
the
Port
Architecture diagrams for Ports A/B and C,
respectively. The direction of data flow for Ports A,
B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a port with the
three least significant bits set to output and the
remainder set to input is shown in Table 28. Since
Port D only contains three pins, the Direction
Register for Port D has only the three least
significant bits active.
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
A pin can be configured as Open Drain if its
corresponding bit in the Drive Select Register is
set to a ‘1’. The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive
Register is set to ‘1’. The default rate is slow slew.
Table 29 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be
configured as Open Drain outputs and which pins
the slew rate can be set for.
Port Data Registers
The Port Data Registers, shown in Table 30, are
used by the microcontroller to write data to or read
data from the ports. Table 30 shows the register
name, the ports having each register type, and
microcontroller access for each register type. The
registers are described below.
Data In
Port pins are connected directly to the Data In
buffer. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
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M8803F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
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