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參數(shù)資料
| 型號： | M8813F3Y-90T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 48/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90T1 |
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M88 FAMILY
52/85
Table 38. JTAG Enable Register
Bit 0
JTAG Enable
0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
X
0
Not used, and should be set to zero.
Bit 4
X
0
Not used, and should be set to zero.
Bit 5
X
0
Not used, and should be set to zero.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
and CSI input features, they are enabled by setting
bits in the PMMR0 and PMMR2 registers.
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in the PMMR0. By setting
the bit to “1”, the Turbo mode is disabled and the
PLDs consume the specified stand-by current
when the inputs are not switching for an extended
time of 70 ns. The propagation delay time will be
increased by 10 ns after the Turbo bit is set to “1”
(turned off) when the inputs change at a composite
frequency of less than 15 MHz. When the Turbo bit
is set to a “0” (turned on), the PLDs run at full
power and speed. The Turbo bit affects the PLD’s
D.C. power, AC power, and propagation delay.
Blocking MCU control signals with PMMR2 bits
can further reduce PLD AC power consumption.
SRAM Standby Mode (Battery Backup)
The M8813Fxx FLASH+PSD supports a battery
backup operation that retains the contents of the
SRAM in the event of a power loss. The SRAM
has a VSTBY pin (PC2) that can be connected to
an external battery. When VCC becomes lower
than VSTBY then the PSD will automatically
connect to VSTBY as a power source to the SRAM.
The SRAM Standby Current (ISTBY) is typically 0.5
A. The SRAM data retention voltage is 2 V
minimum. The battery-on indicator (VBATON)can
be routed to PC4. This signal indicates when the
VCC has dropped below the VSTBY voltage.
The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as
the CSI input. When low, the signal selects and
enables the internal Flash, EEPROM, SRAM, and
I/O for read or write operations involving the
M88x3Fxx FLASH+PSD. A high on the CSI pin will
disable the Flash memory, EEPROM, and SRAM,
and
reduce
the
PSD
power
consumption.
However, the PLD and I/O pins remain operational
when CSI is high.
There may be a timing penalty when using the CSI
pin depending on the speed grade of the PSD that
you are using. See the timing parameter tSLQV in
Table 53A or Table 53B.
Inpu t Clock
The M88x3Fxx FLASH+PSD provides the option
to turn off the CLKIN input to the PLD to save AC
power consumption. The CLKIN is an input to the
PLD AND array and the Output Macrocells.
During Power Down Mode, or, if the CLKIN input
is not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
The CLKIN will be disconnected from the PLD
AND array or the Macrocells by setting bits 4 or 5
to a “1” in PMMR0.
Inpu t Control Signals
The M88x3Fxx FLASH+PSD provides the option
to turn off the input control signals (CNTL0-2, ALE,
and DBE) to the PLD to save AC power
consumption. These control signals are inputs to
the PLD AND array. During Power Down Mode, or,
if any of them are not being used as part of the
PLD logic equation, these control signals should
be disabled to save AC power. They will be
disconnected from the PLD AND array by setting
bits 2, 3, 4, 5, and 6 to a “1” in the PMMR2.
Reset Inpu t
The M88x3Fxx FLASH+PSD has an active low
reset input which loads internal configurations and
clears some of the registers (see Table 36). Figure
35 shows the reset timing requirement. The active
low range has a minimum tNLNH duration. After the
rising edge of reset, the M88x3Fxx FLASH+PSD
remains in the reset state during the tOPR range.
The device must be reset at power-up, prior to
use.
Any Write operation to the EEPROM is
inhibited during the first 5 ms following
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