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參數(shù)資料
| 型號： | M8813F3Y-90T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 47/85頁 |
| 文件大小： | 601K |
| 代理商： | M8813F3Y-90T1 |
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M88 FAMILY
Table 36. Chip Status During Reset and Power Down Mode
Note: 1. The Macrocell Flip-Flop can be cleared or set by the reset input or the PDN signal, depending on the .re and .pr equations that are
defined in the PSDabel file.
2. Bit0 (SRAM_code) and bit7 (PIO_EN) are cleared to zero on any Reset.
Port Configuratio n
Reset
Power Down Mode
MCU I/O
Input
Unchanged
PLD Output
Active
Depend on inputs to PLD
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Port Configuratio n
Reset
Power Down Mode
PMMR, 0 and 2
Cleared
(power up reset only)
Unchanged
Macrocells Flip-Flop
Unchanged1
VM Register2
Initialized based on the
selection in PSDsoft
Configuration menu.
Unchanged
All other registers
Cleared to “0”
Unchanged
s
If the address strobe starts pulsing again, the
PSD will return to normal operation. The PSD
will also return to normal operation if either the
CSI input returns low or the Reset input returns
high.
s
The MCU address/data bus is blocked from all
memories and PLDs.
s
Various signals can be blocked (prior to Power
Down Mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common clock (CLKIN). Note that
blocking CLKIN from the PLDs will not block
CLKIN from the APD unit.
s
All PSD memories enter Standby Mode and are
drawing standby current. However, the PLDs
and I/O ports do not go into Standby Mode
because you don’t want to have to wait for the
logic and I/O to “wake-up” before their outputs
can change. See Table 31 for Power Down
Mode effects on PSD ports.
s
Typical standby current is 50
A for 5 V devices,
and 25
A for 3 V devices. These standby
current values assume that there are no
transitions on any PLD input.
HC11 (or compatible) Users Note
The HC11 turns off its E clock when it sleeps.
Therefore,
if
you
are
using
an
HC11 (or
compatible) in your design, and you wish to use
the Power Down, you must not connect the E clock
to the CLKIN input (PD1). You should instead
connect a cryst al oscillator to the CLKIN input. The
cryst al oscillator frequency must be less than 15
times the frequency of AS. The reason for this is
that if the frequency is greater than 15 times the
frequency of AS, the M88x3Fxx FLASH+PSD will
keep going into Power Down Mode.
Other Power Saving Options
The M88x3Fxx FLASH+PSD offers other reduced
power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby
Table 37. JTAG Port Signals
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
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