參數(shù)資料
型號: M8813F3Y-90T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 58/85頁
文件大?。?/td> 601K
代理商: M8813F3Y-90T1
61/85
M88 FAMILY
Table 46A. CPLD Combinatorial Timing (5 V Range)
Note: 1. Fast Slew Rate output available on PA[ 3: 0], PB[ 3: 0], and PD[ 2: 0].
Table 46B. CPLD Combinatorial Timing (3 V Range Versions)
Note: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
Symbol
Parameter
Conditio ns
-90
-15
Fast PT
Aloc
TURBO
OFF
Slew
Rate1
Unit
Min
Max
Min
Max
tPD
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
25
32
Add 2
Add 10
Sub 2
ns
tEA
CPLD Input to CPLD
Output Enable
26
32
Add 10
Sub 2
ns
tER
CPLD Input to CPLD
Output Disable
26
32
Add 10
Sub 2
ns
tARP
CPLD Register Clear or
Preset Delay
26
33
Add 10
Sub 2
ns
tARPW
CPLD Register Clear or
Preset Pulse Width
20
29
Add 10
ns
tARD
CPLD Array Delay
Any Macrocell
16
22
Add 2
ns
Symbol
Parameter
Conditio ns
-15
PT
Aloc
TURBO
OFF
Slew
Rate1
Unit
Min
Max
tPD
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
48
Add 4
Add 20
Sub 6
ns
tEA
CPLD Input to CPLD
Output Enable
43
Add 20
Sub 6
ns
tER
CPLD Input to CPLD
Output Disable
43
Add 20
Sub 6
ns
tARP
CPLD Register Clear or
Preset Delay
48
Add 20
Sub 6
ns
tARPW
CPLD Register Clear or
Preset Pulse Width
30
Add 20
ns
tARD
CPLD Array Delay
Any Macrocell
29
Add 4
ns
Figu re 41. Combinatorial Timing – PLD
t PD
CPLD INPUT
CPLD
OUTPUT
AI02899
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