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參數(shù)資料
| 型號： | M80C186EB-13 |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| 中文描述： | 16位高性能嵌入式處理器集成（16位高集成嵌入式處理器） |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 855K |
| 代理商： | M80C186EB-13 |
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M80C186EB
BUS CYCLE WAVEFORMS
Figures 19 through 25 present the various bus cy-
cles that are generated by the M80C186EB. What is
shown in the figure is the relationship of the various
bus signals to CLKOUT. These figures along with
the information present in
AC Specifications
allow
the user to determine all the critical timing analysis
needed for a given application.
Figure 19 shows the M80C186EB bus state diagram.
A typical bus cycle will consist of four consecutive
states labeled T1, T2, T3 and T4. A TI state exists
when no bus cycle is pending. A TI state can occur if
the pre-fetch queue is full, the BIU is waiting for the
completion of an effective address calculation, or
the BIU is told to wait for a pending EU bus opera-
tion. The latter case will occur most often during the
sequencing of an interrupt acknowledge or during
the execution of numerics escape instructions.
Aside from TI states, multiple T3 states can occur
during a bus cycle if READY is not returned in time
(or the CSU has been programmed to automatically
insert wait-states). A T3 state will be followed by ei-
ther a T4 state (if a bus cycle is pending), or a TI
state (if no bus cycle is pending). Only multiple T3 or
TI states can exist (i.e., there is no way to extend the
T1, T2 or T4 states).
Figures 20 and 21 present a typical bus read and
write operation respectively. Bus read operations in-
clude memory, I/O, instruction fetch, and refresh
bus cycles. Bus write operations include memory
and I/O bus cycles. The only variation among the
different bus cycles would be the range of address
generated and the state of the status signals.
The Halt bus cycle is shown in Figure 22. Note that
the condition of the AD15:0 pin can be either floating
or driving depending on the operation of the bus cy-
cle that preceded the Halt. The pins will float if the
previous bus cycle was a read, otherwise they will
drive. None of the control signals (e.g., RD, WR,
DEN, etc.) will be activated, however.
Figure 23 shows the sequence of bus cycles run
when an interrupt is acknowledged and the ICU has
been programmed for Cascade Mode. Note the ad-
dress information is not valid for the two bus cycles
run, however, also note that RD and WR are not
generated. Vector information needs to be returned
during the second bus cycle.
Figures 24 and 25 present the operation of bus
HOLD. Figure 24 shows how bus HOLD is entered
and exited under normal operating conditions. Fig-
ure 25 shows the effect specific bus signals have
when a refresh bus cycle request has been generat-
ed and the bus is currently unavailable due to a bus
HOLD.
The effects of READY on bus operation is shown in
Figure 26. READY is useful in extending the bus cy-
cle to meet the various access requirements for
memory and peripheral devices in the system. Addi-
tional T3 states added to the bus cycle have been
appropriately labeled Tw.
271214–17
Figure 19. M80C186EB Bus States
36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M80C186EB-16 | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| M80C186EB-8 | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| M80C186 | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| M80C186XL10 | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL12 | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M80C186EB-16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186EB-8 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL10 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL12 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
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