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| 型號： | M80C186EB-13 |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| 中文描述： | 16位高性能嵌入式處理器集成（16位高集成嵌入式處理器） |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 855K |
| 代理商： | M80C186EB-13 |
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M80C186EB
Table 4. M80C186EB Pin Descriptions
(Continued)
Name
Type
Description
S2:0
O
Bus cycle
Status
are encoded on these pins to provide bus transaction
information. S2:0 are encoded as follows:
H(Z)
R(Z)
P(1)
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Bus Cycle Initiated
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
Passive (no bus activity)
ALE
O
Address Latch Enable
output is used to strobe address information into a
transparent type latch during the address phase of the bus cycle.
H(0)
R(0)
P(0)
BHE
O
Byte High Enable
output to indicate that the bus cycle in progress is
transferring data over the upper half of the data bus. BHE and A0 have the
following logical encoding:
A0 BHE
Encoding
0
0
Word Transfer
0
1
Even Byte Transfer
1
0
Odd Byte Transfer
1
1
Refresh Operation
H(Z)
R(Z)
P(X)
RD
O
ReaD
output signals that the accessed memory or I/O device must drive
data information onto the data bus.
H(Z)
R(Z)
P(1)
WR
O
WRite
output signals that data available on the data bus are to be written
into the accessed memory or I/O device.
H(Z)
R(Z)
P(1)
READY
I
READY
input to signal the completion of a bus cycle. READY must be
active to terminate any M80C186EB bus cycle, unless it is ignored by
correctly programming the Chip-Select Unit.
A(L)
S(L)
DEN
O
Data ENable
output to control the enable of bi-directional transceivers
when buffering a M80C186EB system. DEN is active only when data is to be
transferred on the bus.
H(Z)
R(Z)
P(1)
DT/R
O
Data Transmit/Receive
output controls the direction of a bi-directional
buffer when buffering an M80C186EB system.
H(Z)
R(Z)
P(X)
LOCK
I/O
H(Z)
R(WH)
P(1)
LOCK
output indicates that the bus cycle in progress is not to be
interrupted. The M80C186EB will not service other bus requests (such as
HOLD) while LOCK is active. This pin is configured as a weakly held high
input while RESIN is active and must not be driven low.
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M80C186EB-16 | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| M80C186EB-8 | 16-Bit High-Integration Embedded Processor(16位高集成嵌入式處理器) |
| M80C186 | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| M80C186XL10 | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL12 | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M80C186EB-16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186EB-8 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL10 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL12 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| M80C186XL16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
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