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參數(shù)資料
| 型號(hào)： | M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| 中文描述： | CHMOS高集成16位微處理器 |
| 文件頁數(shù)： | 7/59頁 |
| 文件大小： | 590K |
| 代理商： | M80C186 |
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M80C186
Table 1. M80C186 Pin Description
(Continued)
Symbol
PGA
QFP
Type
Name and Function
HLDA (output)
HOLD (input)
51
50
27
28
O
I
HOLD indicates that another bus master is requesting the
local bus. The HOLD input is active HIGH. HOLD may be
asynchronous with respect to the M80C186 clock. The
M80C186 will issue a HLDA (HIGH) in response to a HOLD
request at the end of T
4
or T
i
. Simultaneous with the
issuance of HLDA, the M80C186 will float the local bus and
control lines. After HOLD is detected as being LOW, the
M80C186 will lower HLDA. When the M80C186 needs to
run another bus cycle, it will again drive the local bus and
control lines.
In Enhanced Mode, HLDA will go low when a DRAM
refresh cycle is pending in the M80C186 and an external
bus master has control of the bus. It will be up to the
external master to relinquish the bus by lowering HOLD so
that the M80C186 may execute the refresh cycle. Lowering
HOLD for four clocks and returning HIGH will insure only
one refresh cycle to the external master. HLDA will
immediately go active after the refresh cycle has taken
place.
UCS
34
44
O
Upper Memory Chip Select is an active LOW output
whenever a memory reference is made to the defined
upper portion (1K–256K block) of memory. This line is not
floated during bus HOLD. The address range activating
UCS is software programmable.
UCS and LCS are sampled upon the rising edge of RES. If
both pins are held low, the M80C186 will enter ONCE
Mode. In ONCE Mode all pins assume a high impedance
state and remain so until a subsequent RESET. UCS has a
weak internal pullup for normal operation.
LCS
33
45
O
Lower Memory Chip Select is active LOW whenever a
memory reference is made to the defined lower portion
(1K–256K) of memory. This line is not floated during bus
HOLD. The address range activating LCS is software
programmable.
UCS and LCS are sampled upon the rising edge of RES. If
both pins are held low, the M80C186 will enter ONCE
Mode. In ONCE Mode all pins assume a high impedance
state and remain so until a subsequent RESET. UCS has a
weak internal pullup for normal operation.
MCS0/PEREQ
MCS1/ERROR
MCS2
MCS3/NPS
38
37
36
35
40
41
42
43
I/O
I/O
O
O
Mid-Range Memory Chip Select signals are active LOW
when a memory reference is made to the defined mid-
range portion of memory (8K–512K). These lines are not
floated during bus HOLD. The address ranges activating
MCS0–3 are software programmable.
In Enhanced Mode, MCS0 becomes a PEREQ input
(Processor Extension Request). When connected to the
Numerics Processor Extension, this input is used to signal
the M80C186 when to make numeric data transfers to and
from the NPX. MCS3 becomes NPS (Numeric Processor
Select) which may only be activated by communication to
the Numerics Processor Extension. MCS1 becomes
ERROR in enhanced mode and is used to signal numerics
coprocessor errors.
7
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