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參數(shù)資料
| 型號(hào)： | M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| 中文描述： | CHMOS高集成16位微處理器 |
| 文件頁數(shù)： | 53/59頁 |
| 文件大?。?/td> | 590K |
| 代理商： | M80C186 |
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M80C186
WAVEFORMS
(Continued)
Typical Output Delay Capacitive Derating
270500–33
Figure 45. Capacitive Derating Curve
M80C186 EXECUTION TIMINGS
A determination of M80C186 program execution tim-
ing must consider both the bus cycles necessary to
prefetch instructions as well as the number of exe-
cution unit cycles necessary to execute instructions.
The following instruction timings represent the mini-
mum execution time in clock cycles for each instruc-
tion. The timings given are based on the following
assumptions:
#
The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.
#
No wait states or bus HOLDs occur.
#
All word-data is located on even-address bound-
aries.
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.
All instructions which involve memory accesses can
require one or two additional clocks above the mini-
mum timings shown due to the asynchronous hand-
shake between the BIU and execution unit.
With a 16-bit BIU, the M80C186 has sufficient bus
performance to ensure that an adequate number of
prefetched bytes will reside in the queue most of the
time. Therefore, actual program execution will not be
substantially greater than that derived from adding
the instruction timings shown.
53
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