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參數(shù)資料
| 型號(hào)： | M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| 中文描述： | CHMOS高集成16位微處理器 |
| 文件頁(yè)數(shù)： | 43/59頁(yè) |
| 文件大小： | 590K |
| 代理商： | M80C186 |
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M80C186
15
E
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PDCON:
Offset F0H
F1
F0
Bits 0–1:
Clock Divisor Select
F1
F0
0
0
1
1
Reserved, read back as zero.
Enable Power Save Mode. Set to zero on RESET.
Division Factor
divide by 1
divide by 4
divide by 8
divide by 16
0
1
0
1
Bits 2–14:
Bit 15:
Figure 44. Power-Save Control Register
Numeric Coprocessor (NPX)
Extension
Three of the mid-range memory chip selects are re-
defined according to Table 16 when using the nu-
merics coprocessor extension. The fourth chip se-
lect, MCS2 functions as in compatible mode, and
may be programmed for activity with ready logic and
wait states accordingly. As in compatible mode,
MCS2 will function for one-fourth a programmed
block size.
Table 16. MCS Assignments
Compatible
Mode
Enhanced Mode
MCS0
MCS1
MCS2
MCS3
PEREQ Processor Extension Request
ERROR NPX Error
MCS2
Mid-Range Chip Select
NPS
Numeric Processor Select
Four port addresses are assigned to the NPX for 16-
bit reads and writes by the M80C186. Table 17
shows the port definitions. These ports are not ac-
cessible by using the M80C186 I/O instructions.
However, numerics operations will cause a PCS line
to be activated if it is properly programmed for this
I/O range.
Table 17. Numerics Coprocessor I/O Port
Assignments
I/O Address
Read Definition
Write Definition
00F8H
00FAH
00FCH
00FEH
Status/Control
Data
reserved
Opcode Status
Opcode
Data
CS:IP, DS:EA
reserved
‘‘ONCE’’ Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the M80C186 has a test
mode available which allows all pins to be placed in
a high-impedance state. ‘‘ONCE’’ stands for ‘‘ON
Circuit Emulation’’. When placed in this mode, the
M80C186 will put all pins in the high-impedance
state until RESET.
The ONCE mode is selected by tying the UCS and
the LCS LOW during RESET. These pins are sam-
pled on the low-to-high transition of the RES pin.
The UCS and the LCS pins have weak internal pull-
up resistors similar to the RD and TEST/BUSY pins
to guarantee proper normal operation.
43
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